MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 395

Manufacturer Part Number

MPC8313ECZQADDC

Microprocessors - MPU 8313 REV2.2 PB ENC EXT

Manufacturer

Freescale Semiconductor

Processor Series

Data Bus Width

Maximum Clock Frequency

Program Memory Size

Data Ram Size

Interface Type

Mounting Style

Package / Case

Number Of Programmable I/os

Number Of Timers

DDR Memory Controller

The fully programmable DDR SDRAM controller supports most JEDEC standard x8, x16, or x32 DDR2

and DDR memories available. In addition, unbuffered and registered DRAM modules are supported.

However, mixing different memory types or unbuffered and registered DRAM modules in the same system

is not supported. Dynamic power management and auto-precharge modes simplify memory system design.

A large set of special features support rapid system debug.

Freescale Semiconductor

Introduction

MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2

In this chapter, the word ‘bank’ refers to a physical bank specified by a chip

select; ‘logical bank’ refers to one of the four or eight sub-banks in each

SDRAM chip. A sub-bank is specified by the 2 or 3 bits on the bank address

(MBA) pins during a memory access.