MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 816
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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15.5.3.6.38 Transmit Jabber Frame Counter (TJBR)
Figure 15-89
Table 15-93
15.5.3.6.39 Transmit FCS Error Counter (TFCS)
Figure 15-90
Table 15-94
15-98
Offset eTSEC1:0x2_4718; eTSEC2:0x2_5718
Reset
Offset eTSEC1:0x2_471C; eTSEC2:0x2_571C
Reset
20–31
20–31
0–19
0–19
Bits
Bits
W
W
R
R
0
0
describes the fields of the TJBR register.
describes the fields of the TFCS register.
Name
Name
TFCS
TJBR
describes the definition for the TJBR register.
describes the definition for the TFCS register.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
—
—
Figure 15-89. Transmit Jabber Frame Counter Register Definition
Reserved
Transmit jabber frame counter. Increments for each oversized transmitted frame with an incorrect
FCS value.
Reserved
Transmit FCS error counter. Increments for every valid sized packet with an incorrect FCS value.
Figure 15-90. Transmit FCS Error Counter Register Definition
Table 15-93. TJBR Field Descriptions
Table 15-94. TFCS Field Descriptions
—
—
All zeros
All zeros
Description
Description
19 20
19 20
Freescale Semiconductor
TJBR
TFCS
Access: Read/Write
Access: Read/Write
31
31
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