MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 109
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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0x0_00B0–
0x0_0040–
0x0_0070–
0x0_00AC
0x0_00FC
0x0_002C
0x0_003C
0x0_005C
0x0_006C
0x0_009C
0x0_00A0
0x0_00A4
0x0_00A8
0x0_0024
0x0_0028
0x0_0030
0x0_0034
0x0_0038
0x0_0060
0x0_0064
0x0_0068
0x0010C
0x00100
0x00104
0x00108
0x00110
0x00114
Offset
eLBC local access window 0 attribute register
(LBLAWAR0)
eLBC local access window 1 base address register
(LBLAWBAR1)
eLBC local access window 1 attribute register
(LBLAWAR1)
eLBC local access window 2 base address register
(LBLAWBAR2)
eLBC local access window 2 attribute register
(LBLAWAR2)
eLBC local access window 3 base address register
(LBLAWBAR3)
eLBC local access window 3 attribute register
(LBLAWAR3)
Reserved
PCI local access window 0 base address register
(PCILAWBAR0)
PCI local access window 0 attribute register (PCILAWAR0)
PCI local access window 1 base address register
(PCILAWBAR1)
PCI local access window 1 attribute register (PCILAWAR1)
Reserved
DDR local access window 0 base address register
(DDRLAWBAR0)
DDR local access window 0 attribute register
(DDRLAWAR0)
DDR local access window 1 base address register
(DDRLAWBAR1)
DDR local access window 1 attribute register
(DDRLAWAR1)
Reserved
System general purpose register low (SGPRL)
System general purpose register high (SGPRH)
System part and revision ID register (SPRIDR)
Reserved
System priority configuration register (SPCR)
System I/O configuration register low (SICRL)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Register
Table 2-2. Memory Map (continued)
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
—
R
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x80B0_0021
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
—
—
—
—
2
3
4
5
6
7
8
Section/Page
5.2.4.5/5-10
5.2.4.6/5-11
5.2.4.5/5-10
5.2.4.6/5-11
5.2.4.7/5-12
5.2.4.8/5-13
5.2.4.7/5-12
5.2.4.8/5-13
5.3.2.1/5-17
5.3.2.2/5-17
5.3.2.3/5-18
5.3.2.4/5-18
5.3.2.5/5-21
5.2.4.4/5-9
5.2.4.3/5-8
5.2.4.4/5-9
5.2.4.3/5-8
5.2.4.4/5-9
5.2.4.3/5-8
5.2.4.4/5-9
—
—
—
—
Memory Map
2-5
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