MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 1154
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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General Purpose I/O (GPIO)
21.2
The following section provides information about GPIO signals.
21.2.1
Table 21-1
21.3
The GPIO has programmable registers that occupy 24 bytes of memory-mapped space. Note that reading
undefined portions of the memory map returns all zeros and writing has no effect.
All GPIO registers are 32 bits wide and are located on 32-bit address boundaries. All addresses used in this
chapter are offsets from the address held in IMMRBAR as defined in
Table 21-2
21-2
GPIO[0:31]
0xC0C
Offset
0xC00
0xC04
0xC08
0xC10
0xC14
•
•
Signal
Open-drain capability on all ports
All ports can optionally generate an interrupt upon changing their state.
Memory Map/Register Definition
External Signal Description
provides detailed descriptions of the external GPIO signals.
shows the memory map of GPIO.
Signals Overview
GPIO direction register (GPDIR)
GPIO open drain register (GPODR)
GPIO data register (GPDAT)
GPIO interrupt event register (GPIER)
GPIO interrupt mask register (GPIMR)
GPIO external interrupt control register (GPICR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
I/O
I/O General purpose I/O. Each signal can be set individually to act as input or output, according to application
needs.
Meaning
Timing Assertion/Negation—Inputs can be asserted completely asynchronously.
Table 21-1. IPIC External Signals—Detailed Signal Descriptions
State
Asserted/Negated—Defined per application.
Outputs are asynchronous to any externally visible clock
Table 21-2. GPIO Register Address Map
Register
Description
Access
R/W
R/W
R/W
R/W
R/W
w1c
Chapter 2, “Memory Map.”
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset Value
Undefined
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