MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 461
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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1
10.3.1.2.2
Figure 10-3
Table 10-7
Freescale Semiconductor
Offset OR0: 0x0_5004
Reset
Reset
17–18
0–16
Refer to
Bits
19
20
W
W
R
R
OR1: 0x0_500c
OR2: 0x0_5014
OR3: 0x0_501c
AM
16
0
BCTLD Buffer control disable. Disables assertion of LBCTL during access to the current memory bank.
Name
CSNT Chip select negation time. Determines when LCS n and LWE are negated during an external memory write
Table 10-5
AM
—
describes OR
shows the bit fields for ORn when the corresponding BRn[MSEL] selects the GPCM machine.
17
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Option Registers (OR
GPCM address mask. Masks corresponding BR n bits. Masking address bits independently allows external
devices of different size address ranges to be used. Address mask bits can be set or cleared in any order in
the field, allowing a resource to reside in more than one area of the address map.
0 Corresponding address bits are masked and therefore don’t care for address checking.
1 Corresponding address bits are used in the comparison between base and transaction addresses.
Reserved
0 LBCTL is asserted upon access to the current memory bank.
1 LBCTL is not asserted upon access to the current memory bank.
access handled by the GPCM, provided that ACS ≠ 00 (when ACS = 00, only LWE is affected by the setting
of CSNT). This helps meet address/data hold times for slow memories and peripherals.
0 LCS n and LWE are negated normally.
1 LCS n and LWE are negated earlier depending on the value of LCRR[CLKDIV].
—
for the OR0 reset value. All other option registers have all bits cleared.
18
[CLKDIV]
LCRR
4 or 8
BCTLD CSNT
n
2
x
19
fields for GPCM mode.
Figure 10-3. Option Registers (OR
Table 10-7. OR
20
CSNT
0
1
1
21
n
ACS
)—GPCM Mode
LCS n and LWE are negated normally.
LCS n and LWE are negated normally.
LCS n and LWE are negated one quarter bus clock cycle earlier.
22
n
—
XACS
GPCM Field Descriptions
23
All zeros
All zeros
AM
Description
24
1
n
) in GPCM Mode
SCY
Meaning
27
SETA
28
Enhanced Local Bus Controller
TRLX
29
Access: Read/Write
EHTR
30
EAD
10-13
15
31
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