MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 745

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

15.5.3.1.4
The interrupt mask register provides control over which possible interrupt events in the IEVENT register
are permitted to participate in generating hardware interrupts to the PIC. All implemented bits in this
Freescale Semiconductor
25–26
Bits
21
22
23
24
27
28
29
30
31
MMWR MII management write completion
MMRD
GRSC
Name
PERR
FGPI
DPE
RXF
FIQ
FIR
—
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Interrupt Mask Register (IMASK)
MII management read completion
0 MII management read not issued or in process.
1 MII management read completed that was initiated by a user through the MII Scan or Read cycle
0 MII management write not issued or in process.
1 MII management write completed that was initiated by a user write to the MIIMCON register.
the user to know if the system has completed the stop and it is safe to write to receive registers (status,
control or configuration registers) that are used by the system during normal operation.
0 Graceful stop not completed.
1 Graceful stop completed.
(RxBD) in that frame was updated. This occurs either if the I (interrupt) bit in the buffer descriptor status word
is set, or an overrun error occurs. The specific receive queue that was updated has its RXF bit set in RSTAT.
0 Frame not received.
1 Frame received.
Reserved
a frame that matches a GPI rule sequence that is specified in the filer. It is synchronized with the setting of
RXF.
0 No filer generated interrupt has occurred.
1 The filer has accepted a frame via a matching rule that the RQFCR[GPI] bit set.
The receive queue filer result is invalid, either because not enough time between frames was available to
find a matching rule, or no entry in the filer table could be matched.
0 Receive queue filer reached a definite result; however, bit FIQ may still be set if a frame was filed to a
1 Receive queue filer was unable to reach a definite result. In this case, bit FIQ is also set if no entry in the
Filed frame to invalid receive queue. This bit indicates that either the receive queue filer chose to DMA a
received frame to a disabled RxBD ring, or that no rule in the filer table could be matched.
0 Received frames filed to valid queues or rejected. Note that a frame may be rejected if the filer has
1 Received frames filed to RxBD rings that are not enabled. The frame is discarded. If bit FIR is also set
which is likely to compromise the validity of recently transferred frames.
0 No parity errors detected.
1 Data held in the FIFO or filer arrays is expected to be corrupted due to a parity error.
unambiguously, due to encapsulated header type fields contradicting each other.
0 Received frame parsed successfully.
1 Received frame parse revealed header inconsistencies.
Graceful receive stop complete. This interrupt is asserted if a graceful receive stop is completed. It allows
Receive frame interrupt. This bit indicates that a frame was received and the last receive buffer descriptor
Filer generated general purpose interrupt on a set of filer rule match. This bit will be set upon reception of
Internal data parity error. This bit indicates that the eTSEC has detected a parity error on its stored data,
Receive frame parse error for TCP/IP off-load. This bit indicates that a received frame could not be parsed
command.
disabled RxBD ring.
filer table could provide a rule match.
insufficient time to reach a conclusive result between frames, in which case bit FIR is set.
this indicates that the filer exhausted all of its table entries without a rule match.
Table 15-8. IEVENT Field Descriptions (continued)
Description
Enhanced Three-Speed Ethernet Controllers
15-27