MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 195
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Figure 4-7
Freescale Semiconductor
The primary clock input to this device is PCI_CLK. This clock is the reference to the system APLL.
125-MHz source
GTX_CLK125
CFG_CLKIN_DIV
USB_CR_CLK_IN
USB_CLK_IN
USB_CR_CLK_OUT
SYS_CLK_IN
125-MHz source
SYS_CR_CLK_IN
SD_REF_CLK/
SD_REF_CLK
SYS_CR_CLK_OUT
Crystal
Crystal
shows the internal distribution of clocks within the device.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
SGMII PHY
Converter
Interface
Protocol
PLL
eTSEC
MPC8313E
USB Mac
USB PHY
mux
/1,/2
PLL
Figure 4-7. Clock Subsystem Block Diagram
System
PLL
e300c3 core
PMC
Divider (÷2)
PCI Clock
Clock
Unit
csb_clk
csb_clk to rest
of the device
ddr_clk
lbc_clk
Core PLL
To local bus
to DDR
memory
controller
Sys Ref
Clock
Divider
DDR
/n
Clock
Divider
LBC
1
0
core_clk
/2
RTC
3
Reset, Clocking, and Initialization
MEMC_MCK
MEMC_MCK
LCLK[0:1]
PCI_CLK_OUT[0:2]
PCI_CLK/
PCI_SYNC_IN
RTC_CLK (32 kHz)
PCI_SYNC_OUT
Local Bus
Memory
Device
DDR
Memory
Device
4-29
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