MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 56
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Table
Number
4-31
4-32
4-33
4-34
4-35
4-36
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16
5-17
5-18
5-19
5-20
5-21
5-22
5-23
5-24
5-25
5-26
5-27
5-28
5-29
5-30
5-31
5-32
5-33
5-34
5-35
lvi
RCR Bit Settings................................................................................................................... 4-36
RCER Bit Settings ................................................................................................................ 4-37
Clock Configuration Registers Memory Map....................................................................... 4-37
System PLL Mode Register Bit Settings .............................................................................. 4-38
OCCR Bit Settings ................................................................................................................ 4-39
SCCR Bit Descriptions ......................................................................................................... 4-40
Local Access Windows Target Interface................................................................................. 5-1
Local Access Windows Example............................................................................................ 5-2
Format of Window Definitions ............................................................................................... 5-3
Local Access Register Memory Map...................................................................................... 5-4
IMMRBAR Bit Settings.......................................................................................................... 5-7
ALTCBAR Bit Settings........................................................................................................... 5-7
LBLAWBAR0–LBLAWBAR3 Bit Settings........................................................................... 5-8
LBLAWBAR0[BASE_ADDR] Reset Value .......................................................................... 5-8
LBLAWAR0–LBLAWAR3 Bit Settings................................................................................. 5-9
LBLAWAR0[EN] Reset Value................................................................................................ 5-9
PCILAWBAR0–PCILAWBAR1 Bit Settings ...................................................................... 5-10
PCILAWBAR0[BASE_ADDR] Reset Value ....................................................................... 5-10
PCILAWAR0–PCILAWAR1 Bit Settings............................................................................. 5-11
PCILAWAR0[EN] Reset Value............................................................................................. 5-11
DDRLAWBAR0–DDRLAWBAR1 Bit Settings .................................................................. 5-12
DDRLAWBAR0[BASE_ADDR] Reset Value ..................................................................... 5-12
DDRLAWAR0–DDRLAWAR1 Bit Settings ........................................................................ 5-13
DDRLAWAR0[EN] Reset Value .......................................................................................... 5-14
Overlapping Local Access Windows .................................................................................... 5-14
System Configuration Register Memory Map ...................................................................... 5-16
SGPRL Bit Settings .............................................................................................................. 5-17
SGPRH Bit Settings .............................................................................................................. 5-17
SPRIDR Bit Settings ............................................................................................................. 5-18
PARTID Coding ................................................................................................................... 5-18
REVID Coding ..................................................................................................................... 5-18
SPCR Bit Settings ................................................................................................................. 5-19
SICRL Bit Settings................................................................................................................ 5-21
SICRH Bit Settings ............................................................................................................... 5-24
SICRH[30–31] Bit Settings .................................................................................................. 5-26
DDRCDR Field Descriptions................................................................................................ 5-27
DDRDSR Field Descriptions ................................................................................................ 5-28
WDT Register Address Map................................................................................................. 5-30
SWCRR Bit Settings ............................................................................................................. 5-31
SWCNR Bit Settings............................................................................................................. 5-32
SWSRR Bit Settings ............................................................................................................. 5-33
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Tables
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