MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 63
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Table
Number
14-2
14-3
14-4
14-5
14-6
14-7
14-8
14-9
14-10
14-11
14-12
14-13
14-14
14-15
14-16
14-17
14-18
14-19
14-20
14-21
14-22
14-23
14-24
14-25
14-26
14-27
14-28
14-29
14-30
14-31
14-32
14-33
14-34
14-35
14-36
14-37
14-38
14-39
14-40
15-1
15-2
Freescale Semiconductor
SEC Address Map................................................................................................................. 14-8
SEC Address Map................................................................................................................. 14-9
Header Dword Bit Definitions ............................................................................................ 14-12
Header Dword Writeback Bit Definitions........................................................................... 14-13
EU_SEL0 and EU_SEL1 Values ........................................................................................ 14-13
Descriptor Types ................................................................................................................. 14-14
Pointer Dword Field Definitions......................................................................................... 14-15
Link Table Field Definitions ............................................................................................... 14-17
Descriptor Format by Type ................................................................................................. 14-18
DEUMR Field Descriptions................................................................................................ 14-20
DEUKSR Field Descriptions .............................................................................................. 14-21
DEURCR Field Descriptions .............................................................................................. 14-22
DEUSR Field Descriptions ................................................................................................. 14-23
DEUISR Field Descriptions................................................................................................ 14-24
DEUICR Field Descriptions ............................................................................................... 14-26
MDEUMR in ‘Old’ Configuration ..................................................................................... 14-29
MDEUMR in ‘New’ Configuration .................................................................................... 14-30
Mode Register—HMAC or SSL-MAC Generated by Single Descriptor........................... 14-31
Mode Register—HMAC Generated Across a Sequence of Descriptors............................. 14-32
MDEURCR Field Descriptions .......................................................................................... 14-33
MDEUSR Field Descriptions.............................................................................................. 14-34
MDEUISR Field Descriptions ............................................................................................ 14-35
MDEUICR Field Descriptions............................................................................................ 14-37
AESUMR Field Descriptions.............................................................................................. 14-41
AES Cipher Modes ............................................................................................................. 14-41
AESURCR Field Descriptions............................................................................................ 14-44
AESUSR Field Descriptions ............................................................................................... 14-44
AESUISR Field Descriptions.............................................................................................. 14-46
AESUICR Field Descriptions ............................................................................................. 14-47
CCCR Field Descriptions.................................................................................................... 14-55
CCPSR Field Descriptions.................................................................................................. 14-57
G_STATE and S_STATE Field Values................................................................................ 14-59
CHN_STATE Field Values.................................................................................................. 14-60
Crypto-Channel Pointer Status Register Error Field Definitions........................................ 14-61
Crypto-Channel Pointer Status Register PAIR_PTR Field Values...................................... 14-61
CDPR Field Descriptions.................................................................................................... 14-62
Fetch FIFO Field Descriptions............................................................................................ 14-63
Field Names in Interrupt Mask, Interrupt Status, and Interrupt Clear Registers ................ 14-70
MCR Field Descriptions ..................................................................................................... 14-74
eTSECn Network Interface Signal Properties ...................................................................... 15-6
eTSEC Signals—Detailed Signal Descriptions .................................................................... 15-8
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Tables
Title
Tables
Number
Page
lxiii
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