MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 169

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

4.1.2
In
functionality is described in
See
Freescale Semiconductor
SYS_CR_CLK_OUT
SYS_CR_CLK_IN
USB_CR_CLK_IN
Table
SYS_CLK_IN
USB_CLK_IN
Figure 4-7
Signal
4-2, some clock signals are specific to blocks within the device. Although some of their
Clock Signals
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
for the internal distribution of clocks in the device.
I/O
O
I
I
I
I
System clock. In PCI host mode, SYS_CLK_IN is the primary input clock. SYS_CLK_IN directly
feeds the PCI output clock dividers and is driven out on the PCI_SYNC_OUT signal for de-skewing
external PCI clocks routing. If the device is used as PCI agent, PCI_CLK can be provided from a
PCI source. In this case, SYS_CLK_IN may no longer be needed and should be tied low. If
SYS_CLK_IN is the clock source, SYS_CR_CLK_IN should be tied low and SYS_CR_CLK_OUT
should be left unconnected.
Requirements Should be tied low if unused, for example in PCI agent mode or when the clock is
Crystal input. SYS_CR_CLK_IN/SYS_CR_CLK_OUT allows the system clock to be provided
using an external crystal oscillator. If a crystal source is used, SYS_CLK_IN should be tied low.
Requirements Should be tied low if unused, for example in PCI agent mode or when the clock is
Crystal output. SYS_CR_CLK_IN/SYS_CR_CLK_OUT allows the system clock to be provided
through an external crystal oscillator. If a crystal source is used, SYS_CLK_IN should be tied low.
Requirements Should be left unconnected if unused, for example in PCI agent mode or when the
USB PHY clock. USB_CLK_IN feeds into the USB PHY PLL.
Requirements Should be tied low if unused, for example when the clock is provided through
USB crystal input. USB_CR_CLK_IN/USB_CR_CLK_OUT allows the USB clock to be provided
using an external crystal oscillator. If a crystal source is used, USB_CLK_IN should be tied low.
Requirements Should be tied low if unused, for example when the clock is provided through
Reset State Always input.
Reset State Always input.
Reset State Always output.
Reset State Always input.
Reset State Always input.
Section 4.4, “Clocking,”
Timing Assertion/Negation—See the hardware specifications for timing information.
Timing Assertion/Negation—See the hardware specifications for timing information.
Timing Assertion/Negation—See the hardware specifications for timing information
Timing Assertion/Negation—See the hardware specifications for timing information.
Timing Assertion/Negation—See the hardware specifications for timing information.
Table 4-2. External Clock Signals
provided through SYS_CR_CLK_IN.
provided through SYS_CLK_IN.
clock is provided through SYS_CLK_IN.
USB_CR_CLK_IN or when derived from the system clock.
USB_CR_CLK_IN or when derived from the system clock.
they are defined in detail in their respective chapters.
Description
Reset, Clocking, and Initialization
4-3