MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 785

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

15.5.3.5
This section describes the MAC registers.
15.5.3.5.1
MACCFG1 is written by the user.
Offset eTSEC1:0x2_4500; eTSEC2:0x2_5500
Table 15-40
Freescale Semiconductor
Reset
Reset
16–22
1–11
\
Bits
12
13
14
15
23
W
W
0
R
R
Soft_Reset
Reset Rx Fun Reset receive function block. This bit is cleared by default.
Reset Rx MC Reset receive MAC control block. This bit is cleared by default.
Reset Tx Fun Reset transmit function block. This bit is cleared by default.
Reset Tx MC Reset transmit MAC control block. This bit is cleared by default.
Soft_Reset
16
Loop Back
0
Name
describes the fields of the MACCFG1 register.
—
—
MAC Registers
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
—
MAC Configuration 1 Register (MACCFG1)
1
Soft reset. This bit is cleared by default. See
Procedure,”
0 Normal operation.
1 Place the entire MAC in reset except for the host interface.
Reserved
0 Normal operation.
1 Place the receive part of the MAC in reset. This block detects control frames and contains the pause
0 Normal operation.
1 Place the transmit part of the MAC in reset. This block multiplexes data and control frame transfers.
0 Normal operation.
1 Place the receive function in reset. This block performs the receive frame protocol.
0 Normal operation.
1 Place the transmit function in reset. This block performs the frame transmission protocol.
Reserved
Loop back. This bit is cleared by default.
0 Normal operation.
1 Loop back the MAC transmit outputs to the MAC receive inputs.
22
timers.
It also responds to XOFF PAUSE control frames.
Loop Back
23
Figure 15-36. MACCFG1 Register Definition
for more information on setting this bit.
Table 15-40. MACCFG1 Field Descriptions
Figure 15-36
—
24 25
—
Rx_Flow Tx_Flow
26
describes the definition for the MACCFG1 register.
11
27
All zeros
All zeros
Sync’d Rx EN
Reset Rx MC Reset Tx MC Reset Rx Fun Reset Tx Fun
Description
Section 15.6.2.2, “Soft Reset and Reconfiguring
12
28
Enhanced Three-Speed Ethernet Controllers
Rx_EN
13
29
Sync’d Tx EN
14
30
Access: Mixed
Tx_EN
15
31
15-67