MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 380
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Integrated Programmable Interrupt Controller (IPIC)
Table 8-20
8.5.13
The bits in the SERSR, shown in
source machine check (mcp) conditions listed in
interrupt controller sets the corresponding SERSR bit.
8-22
Offset 0x40
Reset
10–11
12–15
16–23
24–31
Bits
0–1
2–3
4–7
8–9
W
R
0
MIXB0T MIXB0 priority position IPIC output interrupt type. Defines which type of the IPIC output interrupt signal ( int ,
MIXB1T Same as MIXB0T, but for MIXB1T.
MIXA0T MIXA0 priority position IPIC output interrupt Type. Defines which type of the IPIC output interrupt signal ( int ,
MIXA1T Same as MIXA0T, but for MIXA1T.
Name
EDIx
defines the bit fields of SECNR.
—
—
—
System Error Status Register (SERSR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
cint , or smi ) asserts its request to the core in the MIXB0 priority position. These bits can be changed
dynamically. The definition of MIXB0T is as follows:
00 int request is asserted to the core for MIXB0.
01 smi request is asserted to the core for MIXB0.
10 cint request is asserted to the core for MIXB0.
11 Reserved
Write ignored, read = 0
cint , or smi ) asserts its request to the core in the MIXA0 priority position. These bits can be changed
dynamically. The definition of MIXA0T is as follows:
00 int request is asserted to the core for MIXA0.
01 smi request is asserted to the core for MIXA0.
10 cint request is asserted to the core for MIXA0.
11 Reserved
Write ignored, read = 0
Each bit defines the edge detect mode for the external IRQ n interrupt signals, determines whether the
corresponding IRQ n signal asserts an interrupt request upon either a high-to-low change or low assertion
on the pin. The corresponding IRQ n signal asserts an interrupt request as follows:
0 Low assertionon IRQ n generates an interrupt request (level sensitive).
1 High-to-lowchange on IRQ n generates an interrupt request (edge sensitive).
Write ignored, read = 0
Figure 8-16. System Error Status Register (SERSR)
Figure
Table 8-20. SECNR Field Descriptions
INT n (Implemented bits are listed in
8-16, correspond to the external and internal non-maskable error
Table
All zeros
8-21. When an error interrupt signal is received, the
Description
Table
8-21)
Freescale Semiconductor
Access: Read/write
31
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