MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 855

Manufacturer Part Number

MPC8313ECZQADDC

Microprocessors - MPU 8313 REV2.2 PB ENC EXT

Manufacturer

Freescale Semiconductor

Processor Series

Data Bus Width

Maximum Clock Frequency

Program Memory Size

Data Ram Size

Interface Type

Mounting Style

Package / Case

Number Of Programmable I/os

Number Of Timers

This section describes the reduced ten-bit interface (RTBI) intended to be used between the PHYs and the

eTSEC to implement a reduced-pin count version of a SerDes interface for optical-fiber devices in

1000BASE-SX/LX applications.

signals required to establish eTSEC module connection with a PHY. Note that in RTBI the eTSEC

immediately begins auto-negotiation with the SerDes.

Freescale Semiconductor

The management signals (MDC and MDIO) are common to all of the gigabit Ethernet controllers module

connections in the system, assuming that each PHY has a different management address.

Reduced Ten-Bit Interface (RTBI)

MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2

Transmit Data (TSECn_TXD[3:0]

Receive Data (TSECn_RXD[3:0]

Transmit Control (TX_EN/f(TX_EN,TX_ER))

Receive Control (RX_DV/f(RX_DV,RX_ER))

Gigabit Transmit Clock (TSEC n _GTX_CLK)

Gigabit Reference Clock (GTX_CLK125)

Figure 15-129. eTSEC-RGMII Connection

Figure 15-130

Receive Clock (TSEC n _RX_CLK)

Management Data Clock

Management Data I/O

depicts the basic components of the RTBI including the

Enhanced Three-Speed Ethernet Controllers