MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 256
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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System Configuration
Table 5-53
5.6.6
5.6.6.1
The PIT generates periodic interrupts for use with a real-time operating system or the application software.
It consists of a 32-bit down-counter which is decremented by a clock derived from the CSB clock or from
the PIT clock. The 32-bit counter decrements to zero when loaded with a initial value from the periodic
interval timer load register (PTLDR). After the timer reaches zero, PTEVR[PIF] is set and an interrupt is
generated if PTCNR[PIM] = 1. At the next count cycle, the value in the PTLDR[CLDV] is loaded into the
counter and the process repeats. When a new value is loaded into the PTLDR[CLDV], the PIT is updated,
the prescaler counter is reset, and the counter begins counting. Setting of PTEVR[PIF] generates an
interrupt, that remains pending until PTEVR[PIF] is cleared. If PTEVR[PIF] is set again before being
cleared, the interrupt remains pending until PTEVR[PIF] is cleared. Any write to the PTLDR[CLDV] stops
the current countdown and the count resumes with the new value in PTLDR[CLDV]. If PTCNR[CLEN]
= 0, the PIT cannot count and retains the old count value. PTCTR contain the PIT current value. The PIT
function can be disabled if needed.
Figure 5-38
5-48
Offset 0x10
Reset
0–30
Bits
31
Clocking
W
R
System
Clock
0
PIT
Name
PIF
—
defines the bit fields of PTEVR.
Functional Description
shows the functional PIT block diagram.
PTCNR[CLIN]
Periodic Interval Timer Unit
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Write reserved, read = 0
Periodic interrupt flag bit. Used to indicate the periodic interrupt. Its asserted if the PIT issues an interrupt
after the SPMPIT counter counts to zero. This status bit should be cleared by software.
Figure 5-38. Periodic Interval Timer Functional Block Diagram
Figure 5-37. Periodic Interval Timer Event Register (PTEVR)
PTCNR[CLEN]
Disable
Clock
Table 5-53. PTEVR Bit Settings
PTPSR[PRSC]
Prescaler
32-Bit
All zeros
—
Description
PTLDR[CLDV]
Counter
32-Bit
PTCTR[CNTV]
PTCNR[PIM]
PTEVR[PIF]
Freescale Semiconductor
PERIODIC
Interrupt
Access: w1c
30
w1c
PIF
31
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