MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 316
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Arbiter and Bus Monitor
6.3.2.2
Data time out occurs, if the data tenure was not ended before the specified time-out period (programmed
by ATR[DTO]). In this case, the arbiter performs as follows:
6.3.2.3
The arbiter tracks the transfer error asserted by one of the slaves. In this case, the arbiter performs as
follows:
6.3.2.4
Table 6-10
The arbiter allows address-only (AO) transactions on the bus and the G2 core has ability to issue
address-only (AO) transactions (see HID0 [ABE] in the G2 PowerPC Core Reference Manual, Rev 1). As
there is no advantage in using AO transaction in this system, the bus monitor allows the detection of AO
transactions and treats them as an error.
6-14
4. Issues reset request, MCP or regular interrupt according to AERR[ATO] and AIDR[ATO], if
5. Updates transaction attributes and address of AEATR and AEADR for the first error event.
1. Ends the data tenure by asserting transfer error.
2. Reports on this event in AER[DTO].
3. Issues reset request, MCP or regular interrupt according to AERR[DTO] and AIDR[DTO], if
4. Updates transaction attributes and address of AEATR and AEADR for the first error event.
1. Reports on the event to AER[ETEA].
2. Issues reset request, MCP or regular interrupt according to AERR[ETEA] and AIDR[ETEA] if
3. Updates transaction attributes and address of AEATR and AEADR for the first error event.
enabled by AMR[ATO].
enabled by AMR[DTO].
enabled by AMR[ETEA].
shows transaction types, which are defined as address only:
Data Time Out
Transfer Error
Address Only Transaction Type
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Table 6-10. Address Only Transaction Type Encoding
ttype[0:4]
00000
00100
01000
01100
10000
11000
00001
01001
01101
Clean block
Flush block
Sync
Kill block
eieio
TLB Invalidate
lwarx reservation set
tlbsync
icbi
Bus Commands
Freescale Semiconductor
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