MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 674

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Security Engine (SEC) 2.2
All descriptors other than the final descriptor must output the intermediate message digest for the next
descriptor to reload as MDEU context.
SSL-MAC operations cannot be spread across a sequence of descriptors.
Additional information on descriptors can be found in
14.4.2.3
The MDEU key size register (MDEUKSR), shown in
memory that should be used in HMAC generation. The MDEU supports at most 64 bytes of key. The
MDEU will generate a key size error if the value written to the MDEUKSR exceeds 64 bytes.
14.4.2.4
The MDEU data size register (MDEUDSR), shown in
to be processed. The MDEU decrements this number as it processes data. A read of this register provides
a snapshot of how much data remains to be processed.
The Data Size field is a 21-bit signed number. Values written to this register are added to the current
register value. Multiple writes are allowed. The MDEU processes data when there is a positive value in
this register and there is data available in the private MDEU input FIFO. (Negative values can arise in
inbound processing, when it is necessary to hold back data from the MDEU until the pad length has been
decrypted.)
Since the MDEU does not support bit offsets, bits 61–63 must be written as 0. Furthermore, when the
CONT bit of the MDEU mode register (MDEUMR) is high, the data size must be a multiple of the 512-bit
block size (that is, bits 55–63 must be written as 0). Violating either of these conditions causes a data size
error (DSE in the MDEUISR).
14-32
Reset
Field
Addr
R/W
Table 14-20. Mode Register—HMAC Generated Across a Sequence of Descriptors
MDEU Key Size Register (MDEUKSR)
MDEU Data Size Register (MDEUDSR)
0
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Bits
56
59
60
Figure 14-17. MDEU Key Size Register (MDEUKSR)
HMAC
CONT
Field
INIT
—
Descriptor
1 (on)
1 (on)
1 (on)
First
MDEU 0x3_6008
Figure
Section 14.3, “Descriptor Overview.”
R/W
Figure
0
Descriptor(s)
Middle
14-17, indicates the number of bytes of key
Value
1 (on)
0 (off)
0 (off)
14-18, indicates the number of bits of data
56
Descriptor
57
0 (off)
0 (off)
1 (on)
Final
Key Size (bytes)
Freescale Semiconductor
63