MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 205
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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4.5.2.2
The OCCR shown in
clock modes by writing to this memory mapped register as described below.
Table 4-35
Freescale Semiconductor
Address 0x0_0A04
17–23
26–31
3–15
Bits
Reset
Reset
16
24
25
0
1
2
W
W
R
R
PCICOE
MCKOE,
MCK_
MCK_BOE
BOE
LCLK0OE
LCLK1OE
PCICOE0
PCICOE1
PCICOE2
MCKOE,
16
0
0
1
Name
defines the bit fields of OCCR.
—
—
—
Output Clock Control Register (OCCR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
PCICOE
17
0
1
1
PCI_CLK_OUT0 enable.
0 PCI_CLK_OUT0 signal is disabled (drive constant zero).
1 PCI_CLK_OUT0 signal is enabled to toggle.
PCI_CLK_OUT1 enable.
0 PCI_CLK_OUT1 signal is disabled (drive constant zero).
1 PCI_CLK_OUT1 signal is enabled to toggle.
PCI_CLK_OUT2 enable.
0 PCI_CLK_OUT2 signal is disabled (drive constant zero).
1 PCI_CLK_OUT2 signal is enabled to toggle.
Reserved, should be cleared
Enable/Disable MCK pin clock out
0 Disable MCK and MCK
1 Enable MCK and MCK
Reserved
Enable/Disable LCLK[0] pin clock out
0 Disable LCLK[0]
1 Enable LCLK[0]
Enable/Disable LCLK[1] pin clock out
0 Disable LCLK[1]
1 Enable LCLK[1]
Reserved
PCICOE
Figure
2
2
0
Figure 4-14. Output Clock Control Register (OCCR)
4-14, controls the device output clocks. It is possible to control some output
0
3
—
0
Table 4-35. OCCR Bit Settings
0
0
All zeros
23
0
Description
LCLK
0OE
24
1
—
LCLK
1OE
25
1
26
0
Reset, Clocking, and Initialization
0
0
Access: Read/Write
—
0
0
4-39
15
31
0
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