MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 828

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Three-Speed Ethernet Controllers
If, at any stage, the value written to RFBPTRn matches that of the respective RBPTRn the eTSEC free BD
calculation assumes that the ring is now completely empty. For more information on the recommended use
of these registers, see
Figure 15-104
Table 15-108
15.5.3.10 Hardware Assist for IEEE1588 Compliant Timestamping
IEEE 1588 compliant timestamping on this device is accomplished using the per-port transmit
timestamping registers within each Ethernet controller memory space (See
Timestamp Identification Register
Register
within the memory space for eTSEC1. Because the common 1588 timestamping registers exist within the
eTSEC1 memory space, the eTSEC1 controller must remain enabled in order to use 1588 timestamping
for any Ethernet port.
15.5.3.10.1 Timer Control Register (TMR_CTRL)
This register is used to reset, configure, and initialize the eTSEC precision timer clock. The control of all
timer function is performed via programming eTSEC1.The register in eTSEC1 is shared for all eTSECs.
Figure 15-7 describes the definition for the TMR_CTRL register.
Register fields not described below are reserved.
15-110
Offset eTSEC1:0x2_4C40+8× n ; eTSEC2:0x2_5C40+8× n
Reset
29–31
0–28 RFBPTR Pointer to the last free BD in RxBD Ring n . When RBASE n is updated, eTSEC initializes RFBPTR n
Bits
W
R
(TMR_TXTS1–2_H/L).”) in conjunction with the following common registers, which are located
0
Name
—
describes the fields of the RFBPTRn registers.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
describes the definition for the RFBPTRn register.
to the value in the corresponding RBASE n .
Software may update this register at any time to inform the eTSEC the location of the last free BD
in the ring. Note that the 3 least-significant bits of this register are read only and zero.
Reserved.
Section 15.6.5.1, “Back Pressure Determination through Free
Figure 15-104. RFBPTR0–RFBPTR7 Register Definition
Table 15-108. RFBPTR0–RFBPTR7 Field Descriptions
(TMR_TXTS1–2_ID),” and
RFBPTR n
All zeros
Description
Section 15.5.3.2.12, “Transmit Timestamp
Section 15.5.3.2.11, “Transmit
Buffers.”
Freescale Semiconductor
Access: Read/Write
28 29
—
31