MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 111

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Freescale Semiconductor
General Purpose (Global) Timer Module 2:
All registers defined for GTM1 are also defined for GTM2; the base address of GTM2 registers is 0x0_06 nn .
0x05–0x0F
Offset
0x1C
0x2C
0x3C
0x0C
0x1A
0x1E
0x2A
0x2E
0x3A
0x3E
0x04
0x10
0x12
0x14
0x16
0x18
0x20
0x22
0x24
0x26
0x28
0x30
0x32
0x34
0x36
0x38
0x00
0x04
0x08
0x10
Timer 3 and 4 global timers configuration register
(GTCFR2)
Reserved
Timer 1 global timers mode register (GTMDR1)
Timer 2 global timers mode register (GTMDR2)
Timer 1 global timers reference register (GTRFR1)
Timer 2 global timers reference register (GTRFR2)
Timer 1 global timers capture register (GTCPR1)
Timer 2 global timers capture register (GTCPR2)
Timer 1 global timers counter register (GTCNR1)
Timer 2 global timers counter register (GTCNR2)
Timer 3 global timers mode register (GTMDR3)
Timer 4 global timers mode register (GTMDR4)
Timer 3 global timers reference register (GTRFR3)
Timer 4 global timers reference register (GTRFR4)
Timer 3 global timers capture register (GTCPR3)
Timer 4 global timers capture register (GTCPR4)
Timer 3 global timers counter register (GTCNR3)
Timer 4 global timers counter register (GTCNR4)
Timer 1 global timers event register (GTEVR1)
Timer 2 global timers event register (GTEVR2)
Timer 3 global timers event register (GTEVR3)
Timer 4 global timers event register (GTEVR4)
Timer 1 global timers prescale register (GTPSR1)
Timer 2 global timers prescale register (GTPSR2)
Timer 3 global timers prescale register (GTPSR3)
Timer 4 global timers prescale register (GTPSR4)
System global interrupt configuration register (SICFR)
System regular interrupt vector register (SIVCR)
System internal interrupt pending register (SIPNR_H)
System internal interrupt pending register (SIPNR_L)
System internal interrupt group A priority register
(SIPRR_A)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Integrated Programmable Interrupt Controller (IPIC)
Register
Table 2-2. Memory Map (continued)
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
w1c
—
R
R
R
R
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0530_9770
0xFFFF
0xFFFF
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0003
Reset
0x00
—
Section/Page
5.7.5.1/5-55
5.7.5.2/5-58
5.7.5.3/5-59
5.7.5.4/5-59
5.7.5.5/5-60
5.7.5.2/5-58
5.7.5.3/5-59
5.7.5.4/5-59
5.7.5.5/5-60
5.7.5.6/5-60
5.7.5.7/5-61
8.5.3/8-11
8.5.3/8-11
8.5.4/8-13
8.5.1/8-7
8.5.2/8-9
—
Memory Map
2-7