MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 1130

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

DUART
UIIR indicates whether the FIFOs are enabled. UIIR[IID3] is set only for FIFO mode interrupts. The
character time-out interrupt occurs when no characters have been removed from or input to the receiver
FIFO during the last four character times and at least one character is in the receiver FIFO. The character
time-out interrupt (controlled by UIIR[IID]) is cleared when URBR is read. See
“Interrupt ID Registers (UIIR1 and UIIR2).”
UIIR[FE] indicates whether FIFO mode is enabled.
18.4.5.2
UDSR[RXRDY] reflects the status of the receiver FIFO or URBR. In mode 0 (UFCR[DMS] is cleared),
UDSR[RXRDY] is cleared when at least one character is in the receiver FIFO or URBR; it is set when
there are no more characters in the receiver FIFO or URBR. This occurs regardless of the UFCR[FEN]
setting. In mode 1 (UFCR[DMS] and UFCR[FEN] are set), UDSR[RXRDY] is cleared when the trigger
level or a time-out has been reached; it is set when there are no more characters in the receiver FIFO.
UDSR[TXRDY] reflects the status of the transmitter FIFO or UTHR. In mode 0 (UFCR[DMS] is cleared),
UDSR[TXRDY] is cleared when there are no characters in the transmitter FIFO or UTHR; it is set after
the first character is loaded into the transmitter FIFO or UTHR. This occurs regardless of the UFCR[FEN]
setting. In mode 1 (UFCR[DMS] and UFCR[FEN] are set), UDSR[TXRDY] is cleared when there are no
characters in the transmitter FIFO or UTHR; it is set when the transmitter FIFO is full.
See
USDR[RXRDY] and USDR[TXRDY] bits.
18.4.5.3
An interrupt is active when DUART interrupt ID register bit 0 (UIIR[0]), is cleared. UIER is used to mask
specific interrupt types. See
When the interrupts are disabled in UIER, polling software can not use UIIR[0] to determine whether the
UART is ready for service. Software must monitor the appropriate ULSR and UMSR bits. UIIR[0] can be
used for polling if the interrupts are enabled in UIER.
18.5
The following requirements must be met for DUART accesses:
A system reset puts the DUART registers to a default state. Before the interface can transfer serial data,
the following initialization steps are recommended:
18-22
•
•
1. Update the programmable interrupt controller (PIC) DUART channel interrupt vector source
2. Set data attributes and control bits in the ULCR, UFCR, UAFR, UMCR, UDLB, and UDMB.
Section 18.3.1.13, “DMA Status Registers (UDSR1 and UDSR2),”
All DUART registers must be mapped to a cache-inhibited and guarded area. (That is, the WIMG
setting in the MMU needs to be 0b01x1.)
All DUART registers are 1 byte wide. Reads and writes to these registers must be byte-length
operations.
registers.
DUART Initialization/Application Information
DMA Mode Select
Interrupt Control Logic
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Section 18.3.1.4, “Interrupt Enable Registers (UIER1 and UIER2).”
for a complete description of the
Section 18.3.1.5,
Freescale Semiconductor