MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 763
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Table 15-21
15.5.3.2.8
The TBDBPH register is written by the user with the most significant address bits common to all TxBD
buffer addresses, TxBD[Data Buffer Pointer]. As a consequence, all Tx buffers must be placed in a 4
gigabyte segment of memory whose base address is prefixed by the bits in TBDBPH. The TxBD ring itself
can reside in a different memory region (based at TBASEH).
TBDBPH register.
Table 15-22
15.5.3.2.9
TBPTR0–TBPTR7 each contains the low-order 32 bits of the next transmit buffer descriptor address for
their respective TxBD ring.
of their ring’s associated TBASE when the TBASE register is written by software. Software must not write
TBPTR0–TBPTR7 while eTSEC is actively transmitting frames. However, TBPTR0– TBPTR7 can be
modified when the transmitter is disabled or when no Tx buffer is in use (after a GRACEFUL STOP
Freescale Semiconductor
16–23
24–31
28–31
8–15
0–27
Bits
Bits
0–7
Offset
Reset
W
R
Name
TBDBPH Most significant bits common to all data buffer addresses contained in TxBDs. The user must initialize
WT5
WT6
WT7
WT4
0
Name
eTSEC1:0x2_4180; eTSEC2:0x2_5180
—
describes the fields of the TR47WT register.
describes the fields of the TBDBPH register.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Transmit Data Buffer Pointer High Register (TBDBPH)
Transmit Buffer Descriptor Pointers 0–7 (TBPTR0–TBPTR7)
Weighting value for TxBD ring 4 when TCTRL[TXSCHED] = 10. On each round of the Tx scheduler, a
minimum of WT4 × 64 bytes of data are scheduled for transmission from TxBD ring 4. Clearing this field
prevents transmission.
Weighting value for TxBD ring 5 when TCTRL[TXSCHED] = 10. On each round of the Tx scheduler, a
minimum of WT5 × 64 bytes of data are scheduled for transmission from TxBD ring 5. Clearing this field
prevents transmission.
Weighting value for TxBD ring 6 when TCTRL[TXSCHED] = 10. On each round of the Tx scheduler, a
minimum of WT6 × 64 bytes of data are scheduled for transmission from TxBD ring 6. Clearing this field
prevents transmission.
Weighting value for TxBD ring 7 when TCTRL[TXSCHED] = 10. On each round of the Tx scheduler, a
minimum of WT7 × 64 bytes of data are scheduled for transmission from TxBD ring 7. Clearing this field
prevents transmission.
Reserved
TBDBPH before enabling the eTSEC transmit function.
Figure 15-18
Figure 15-17. TBDBPH Register Definition
Table 15-22. TBDBPH Field Descriptions
Table 15-21. TR47WT Field Descriptions
describes the TBPTR registers. These registers takes on the value
—
All zeros
Description
Description
Figure 15-17
Enhanced Three-Speed Ethernet Controllers
describes the definition for the
Access: Read/Write
27 28
TBDBPH
15-45
31
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