MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 989

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

16.5.5.4
The last five DWords of a queue element transfer descriptor make up an array of physical memory address
pointers. These pointers reference the individual pages of a data buffer.
System software initializes the Current Offset field to the starting offset into the current page, where
current page is selected with the value in the C_Page field.
Freescale Semiconductor
31–12
11–0
Bits
Bits
Current Offset
Buffer Pointer
(Pages 1–4)
(Page 0)/
(page n )
Name
Name
qTD Buffer Page Pointer List
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
—
Each element in the list is a 4K page aligned physical memory address. The lower 12 bits in each
pointer are reserved (except for the first one), as each memory pointer must reference the start of
a 4K page. The field C_Page specifies the current active pointer. When the transfer element
descriptor is fetched, the starting buffer address is selected using C_Page (similar to an array index
to select an array element). If a transaction spans a 4K buffer boundary, the host controller must
detect the page-span boundary in the data stream, increment C_Page and advance to the next
buffer pointer in the list, and conclude the transaction via the new buffer pointer.
Reserved in all pointers except the first one (that is, Page 0). The host controller should ignore all
reserved bits. For the page 0 current offset interpretation, this field is the byte offset into the current
page (as selected by C_Page). The host controller is not required to write this field back when the
qTD is retired. Software should ensure the reserved fields are initialized to zeros.
Table 16-55. qTD Token (DWord 2) (continued)
1
0
Table 16-56. qTD Buffer Pointer
Split transaction state (SplitXstate). This bit is ignored by the host controller
unless the QH[EPS] field indicates a full- or low-speed endpoint. When a full-
or low-speed device, the host controller uses this bit to track the state of the
split- transaction. The functional requirements of the host controller for
managing this state bit and the split transaction protocol depends on whether
the endpoint is in the periodic or asynchronous schedule. The bit encodings
are:
0 Do start split. This value directs the host controller to issue a start split
1 Do complete split. This value directs the host controller to issue a Complete
Ping state (P)/ERR. If the QH[EPS] field indicates a high-speed device and
the PID Code indicates an OUT endpoint, then this is the state bit for the Ping
protocol. The bit encodings are:
0 Do OUT. This value directs the host controller to issue an OUT PID to the
1 Do Ping. This value directs the host controller to issue a PING PID to the
If the QH[EPS] field does not indicate a high-speed device, then this field is
used as an error indicator bit. It is set by the host controller whenever a
periodic split-transaction receives an ERR handshake.
transaction to the endpoint.
split transaction to the endpoint.
endpoint.
endpoint.
Description
Description
Universal Serial Bus Interface
16-61