MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 1190
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Glossary-2
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Bus master. The owner of the address or data bus; the device that initiates or requests the
Cache. High-speed memory containing recently accessed data or instructions (subset of
Cache block. A small region of contiguous memory that is copied from memory into a
Cache coherency. An attribute wherein an accurate and common view of memory is
Cache flush. An operation that removes from a cache any data from a specified address
Caching-inhibited. A memory update policy in which the cache is bypassed and the load
Cast out. A
Changed bit. One of two page history bits found in each page table entry (PTE). The
Clean. An operation that causes a cache block to be written to memory, if modified, and
Clear. To cause a bit or bit field to register a value of zero. See also Set.
Context synchronization. An operation that ensures that all instructions in execution
Copy-back operation. A cache operation in which a cache line is copied back to memory
transaction.
main memory).
cache. The size of a cache block may vary among processors; the maximum block
size is one page. In Power Architecture processors, cache coherency is maintained
on a cache-block basis. Note that the term ‘cache block’ is often used
interchangeably with ‘cache line.’
provided to all devices that share the same memory system. Caches are coherent
if a processor performing a read from its cache is supplied with data corresponding
to the most recent value written to memory or to another processor’s cache.
range. This operation ensures that any modified data within the specified address
range is written back to main memory. This operation is generated typically by a
Data Cache Block Flush (dcbf) instruction.
or store is performed to or from main memory.
block to be replaced.
processor sets the changed bit if any store is performed into the page. See also
Page access history bits
then left in a valid, unmodified state in the cache.
complete past the point where they can produce an exception, that all instructions
in execution complete in the context in which they began execution, and that all
subsequent instructions are
synchronization may result from executing specific instructions (such as isync or
rfi) or when certain events occur (such as an exception).
to enforce cache coherency. Copy-back operations consist of snoop push-out
operations and cache cast-out operations.
cache block
that must be written to memory when a cache miss causes a cache
and
fetched
Referenced
and executed in the new context. Context
bit.
Freescale Semiconductor
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