MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 22
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Paragraph
Number
14.4.2.13
14.4.3
14.4.3.1
14.4.3.2
14.4.3.3
14.4.3.4
14.4.3.5
14.4.3.6
14.4.3.7
14.4.3.8
14.4.3.9
14.4.3.9.1
14.4.3.9.2
14.4.3.9.3
14.4.3.9.4
14.4.3.9.5
14.4.3.9.6
14.5
14.5.1
14.5.1.1
14.5.1.2
14.5.1.3
14.5.1.4
14.5.1.5
14.5.2
14.5.2.1
14.5.2.2
14.5.2.3
14.6
14.6.1
14.6.2
14.6.2.1
14.6.2.2
14.6.2.3
14.6.3
14.6.4
14.6.4.1
14.6.4.2
14.6.4.3
14.6.4.4
14.6.4.5
xxii
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Channel ........................................................................................................................ 14-53
Controller ..................................................................................................................... 14-64
Advanced Encryption Standard Execution Unit (AESU)........................................ 14-40
Channel Registers .................................................................................................... 14-55
Channel Interrupts.................................................................................................... 14-64
Assignment of EUs to Channel................................................................................ 14-65
Bus Interface ............................................................................................................ 14-65
Controller Interrupts ................................................................................................ 14-66
Controller Registers ................................................................................................. 14-67
MDEU FIFOs ...................................................................................................... 14-40
AESU Mode Register (AESUMR)...................................................................... 14-40
AESU Key Size Register (AESUKSR) ............................................................... 14-42
AESU Data Size Register (AESUDSR) .............................................................. 14-43
AESU Reset Control Register (AESURCR) ....................................................... 14-43
AESU Status Register (AESUSR)....................................................................... 14-44
AESU Interrupt Status Register (AESUISR)....................................................... 14-45
AESU Interrupt Control Register (AESUICR).................................................... 14-47
AESU End-of-Message Register (AESUEMR) .................................................. 14-48
AESU Context Registers ..................................................................................... 14-49
Crypto-Channel Configuration Register (CCCR) ............................................... 14-55
Crypto-Channel Pointer Status Register (CCPSR).............................................. 14-57
Crypto-Channel Current Descriptor Pointer Register (CDPR) ........................... 14-62
Fetch FIFO (FF)................................................................................................... 14-62
Descriptor Buffer (DB)........................................................................................ 14-63
Channel Done Interrupt ....................................................................................... 14-64
Channel Error Interrupt........................................................................................ 14-64
Channel Reset ...................................................................................................... 14-64
Arbitration for Use of the Controller and Buses.................................................. 14-65
Master Read ......................................................................................................... 14-66
Master Write ........................................................................................................ 14-66
EU Assignment Status Register (EUASR) .......................................................... 14-67
Interrupt Mask Register (IMR)............................................................................ 14-68
Interrupt Status Register (ISR) ............................................................................ 14-70
Interrupt Clear Register (ICR) ............................................................................. 14-71
Identification Register (ID).................................................................................. 14-73
Context for CBC Mode.................................................................................... 14-50
Context for Counter Mode............................................................................... 14-50
Context for SRT Mode .................................................................................... 14-50
Context for CCM Mode................................................................................... 14-50
AESU Key Registers ....................................................................................... 14-53
AESU FIFOs.................................................................................................... 14-53
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