MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 457

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

10.3.1
This section provides a detailed description of the eLBC configuration, status, and control registers with
detailed bit and field descriptions.
Address offsets in the eLBC address range that are not defined in
reading or writing. Similarly, only zero should be written to reserved bits of defined registers, as writing
ones can have unpredictable results in some cases.
Bits designated as write-one-to-clear are cleared only by writing ones to them. Writing zeros to them has
no effect.
Freescale Semiconductor
0x0C8–
0x0D8–
0x0F8–
0x0BC
0x0CC
0x0DC
0x0EC
0x0B8
0x0C0
0x0C4
0x0D0
0x0D4
0x0E0
0x0E4
0x0E8
0x0FC
0x10C
0x0F0
0x0F4
0x100
0x104
0x108
Offset
Register Descriptions
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
LTEIR—Transfer error interrupt register
LTEATR—Transfer error attributes register
LTEAR—Transfer error address register
LTECCR—Transfer error ECC register
Reserved
LBCR—Configuration register
LCRR—Clock ratio register
Reserved
FMR—Flash mode register
FIR—Flash instruction register
FCR—Flash command register
FBAR—Flash block address register
FPAR—Flash page address register
FBCR—Flash byte count register
Reserved
FECC0—Flash ECC block 0 register
FECC1—Flash ECC block 1 register
FECC2—Flash ECC block 2 register
FECC3—Flash ECC block 3 register
Table 10-3. Enhanced Local Bus Controller Registers (continued)
Enhanced Local Bus Controller
Register
—Block Base Address 0x0_5000
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
w1c
—
—
—
R
R
R
R
Table 10-3
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0004_0000
0x8000_0008
0x0000_0 n 00
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
should not be accessed for
Reset
—
—
—
Enhanced Local Bus Controller
10.3.1.11/10-28
10.3.1.12/10-29
10.3.1.13/10-30
10.3.1.14/10-30
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