MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 955
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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31–30
27–26 PSPD Port speed. This read-only register field indicates the speed at which the port is operating.
Bits
29
28
25
24
23
22
21
WKOC Wake on over-current enable. Writing this bit to a one enables the port to be sensitive to over-current
WKDS Wake on disconnect enable. Writing this bit to a one enables the port to be sensitive to device disconnects as
PHCD PHY low power suspend. This bit is not defined in the EHCI specification.
Name
PFSC Port force full-speed connect. Used to disable the chirp sequence that allows the port to identify itself as a HS
PTS
—
—
—
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Port transceiver select. This register bit is used to control which parallel transceiver interface is selected.
00 UTMI parallel interface
01 Reserved, should be cleared
10 ULPI parallel interface
11 Reserved
This bit is not defined in the EHCI specification.
Reserved, should be cleared
Reserved
This bit is not defined in the EHCI specification.
00 Full-speed
01 Low-speed
10 High-speed
11 Undefined
Reserved, should be cleared
port. This is useful for testing FS configurations with a HS host, hub or device.
0 Allow the port to identify itself as high speed.
1 Force the port to only connect at full speed.
This bit is not defined in the EHCI specification.
This bit is for debugging purposes.
Host mode:
Device mode:
0 Normal PHY operation.
1 Signal the PHY to enter low power suspend mode
Reading this bit indicates the status of the PHY.
Note: If there is no clock connected to the USBDR_CLK signals, PHCD must be set and the following
registers should not be written: DEVICE_ADDR/PERIODICLISTBASE, PORTSC, ENDPTCTRL0,
ENDPTCTRL1, ENDPTCTRL2.
conditions as wake-up events.
This field is zero if Port Power (PP) is zero.
This bit is (OTG/host mode only) for use by an external power control circuit.
wake-up events.
This field is zero if Port Power(PP) is zero or in device mode.
This bit is (OTG/host mode only) for use by an external power control circuit.
• The PHY can be put into low power suspend—when the downstream device has been put into suspend
• The PHY can be put into low power suspend—when the device is not running (USBCMD[RS] = 0b) or
mode or when no downstream device is connected. Low power suspend is completely under the control of
software.
suspend signaling is detected on the USB. Low power suspend will be cleared automatically when the
resume signaling has been detected or when forcing port resume.
Table 16-23. PORTSC Register Field Descriptions
Description
Universal Serial Bus Interface
16-27
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