MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 804
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Enhanced Three-Speed Ethernet Controllers
15.5.3.6.14 Receive Pause Frame Packet Counter (RXPF)
Figure 15-65
Table 15-69
15.5.3.6.15 Receive Unknown Opcode Packet Counter (RXUO)
Figure 15-66
Table 15-70
15-86
16–31
0–15
Bits
Offset eTSEC1:0x2_46B4; eTSEC2:0x2_56B4
Reset
Offset eTSEC1:0x2_46B8; eTSEC2:0x2_56B8
Reset
16–31
0–15
Bits
W
W
R
R
RXUO
Name
0
0
—
describes the fields of the RXPF register.
describes the fields of the RXUO register.
Name
RXPF
describes the definition for the RXPF register.
describes the definition for the RXUO register.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
—
Figure 15-66. Receive Unknown OPCode Packet Counter Register Definition
Reserved
Receive unknown opcode counter. Increments each time a MAC control frame is received which contains
an opcode other than PAUSE, but the frame has valid CRC and length 64 to 1518 (non VLAN) or 1522
(VLAN).
Figure 15-65. Receive Pause Frame Packet Counter Register Definition
Reserved
received with valid CRC and of lengths 64 to 1518 (non VLAN) or 1522 (VLAN).
Receive PAUSE frame packet counter. Increments each time a PAUSE MAC control frame is
—
—
Table 15-70. RXUO Field Descriptions
Table 15-69. RXPF Field Descriptions
All zeros
All zeros
15 16
15 16
Description
Description
RXUO
RXPF
Freescale Semiconductor
Access: Read/Write
Access: Read/Write
31
31
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