MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 39
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Freescale Semiconductor
s
MPC8313E Block Diagram .................................................................................................... 1-1
MPC8313E Integrated e300c3 Core Block Diagram.............................................................. 1-9
Integrated Security Engine Functional Blocks...................................................................... 1-10
USB Controllers Port Configuration..................................................................................... 1-13
MPC8313E Serving as the Main CPU in a Low-End Printer Application ........................... 1-19
MPC8313E I/O Processor Implementation in a High-End Printer Application ................... 1-20
IEEE Std. 1588 in Test and Measurement ............................................................................ 1-21
IEEE Std. 1588 in Industrial Control .................................................................................... 1-22
MPC8313E as a WLAN Access Point .................................................................................. 1-23
MPC8313E as a Media Server .............................................................................................. 1-24
MPC8313E Signal Groupings (1 of 2).................................................................................... 3-2
MPC8313E Signal Groupings (2 of 2).................................................................................... 3-3
Power-On Reset Flow ............................................................................................................. 4-8
Hard Reset Flow...................................................................................................................... 4-9
Reset Configuration Word Low Register (RCWLR) ............................................................ 4-13
Reset Configuration Word High Register (RCWHR) ........................................................... 4-14
EEPROM Data Format for Reset Configuration Words Preload Command ........................ 4-24
EEPROM Contents ............................................................................................................... 4-25
Clock Subsystem Block Diagram ......................................................................................... 4-29
Reset Status Register (RSR).................................................................................................. 4-33
Reset Mode Register (RMR)................................................................................................. 4-35
Reset Protection Register (RPR)........................................................................................... 4-35
Reset Control Register (RCR)............................................................................................... 4-36
Reset Control Enable Register (RCER) ................................................................................ 4-37
System PLL Mode Register .................................................................................................. 4-38
Output Clock Control Register (OCCR) ............................................................................... 4-39
System Clock Control Register (SCCR) ............................................................................... 4-40
Local Memory Map Example ................................................................................................. 5-2
Internal Memory Map Registers’ Base Address Register (IMMRBAR)................................ 5-6
Alternate Configuration Base Address Register (ALTCBAR) ............................................... 5-7
LBC Local Access Window n Base Address Registers (LBLAWBAR0–LBLAWBAR3) .... 5-8
LBC Local Access Window n Attributes Registers (LBLAWAR0–LBLAWAR3) ................ 5-9
PCI Local Access Window n Base Address Registers (PCILAWBAR0–PCILAWBAR1) . 5-10
PCI Local Access Window n Attributes Registers (PCILAWAR0–PCILAWAR1).............. 5-11
DDR Local Access Window n Base Address Registers (DDRLAWBAR0–
DDR Local Access Window n Attributes Registers (DDRLAWAR0–DDRLAWAR1) ....... 5-13
System General Purpose Register Low (SGPRL)................................................................. 5-17
DDRLAWBAR1) ............................................................................................................. 5-12
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Figures
Title
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Number
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