MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 13

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Paragraph
Number
9.3.2
9.3.2.1
9.3.2.2
9.3.2.3
9.4
9.4.1
9.4.1.1
9.4.1.2
9.4.1.3
9.4.1.4
9.4.1.5
9.4.1.6
9.4.1.7
9.4.1.8
9.4.1.9
9.4.1.10
9.4.1.11
9.4.1.12
9.4.1.13
9.4.1.14
9.4.1.15
9.4.1.16
9.4.1.17
9.5
9.5.1
9.5.1.1
9.5.2
9.5.3
9.5.4
9.5.4.1
9.5.5
9.5.6
9.5.7
9.5.8
9.5.8.1
9.5.8.2
9.5.8.2.1
9.5.9
9.5.10
Freescale Semiconductor
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Memory Map/Register Definition ................................................................................... 9-8
Functional Description................................................................................................... 9-29
Detailed Signal Descriptions ....................................................................................... 9-5
Register Descriptions................................................................................................... 9-9
DDR SDRAM Interface Operation............................................................................ 9-32
DDR SDRAM Address Multiplexing........................................................................ 9-34
JEDEC Standard DDR SDRAM Interface Commands ............................................. 9-37
DDR SDRAM Interface Timing................................................................................ 9-39
DDR SDRAM Mode-Set Command Timing............................................................. 9-42
DDR SDRAM Registered DIMM Mode ................................................................... 9-43
DDR SDRAM Write Timing Adjustments ................................................................ 9-43
DDR SDRAM Refresh .............................................................................................. 9-44
DDR Data Beat Ordering........................................................................................... 9-48
Page Mode and Logical Bank Retention ................................................................... 9-48
Memory Interface Signals........................................................................................ 9-5
Clock Interface Signals............................................................................................ 9-7
Debug Signals.......................................................................................................... 9-8
Chip Select Memory Bounds (CSn_BNDS)............................................................ 9-9
Chip Select Configuration (CSn_CONFIG).......................................................... 9-10
DDR SDRAM Timing Configuration 3 (TIMING_CFG_3)................................. 9-11
DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)................................. 9-12
DDR SDRAM Timing Configuration 1 (TIMING_CFG_1)................................. 9-14
DDR SDRAM Timing Configuration 2 (TIMING_CFG_2)................................. 9-16
DDR SDRAM Control Configuration (DDR_SDRAM_CFG)............................. 9-18
DDR SDRAM Control Configuration 2 (DDR_SDRAM_CFG_2)...................... 9-21
DDR SDRAM Mode Configuration (DDR_SDRAM_MODE)............................ 9-22
DDR SDRAM Mode 2 Configuration (DDR_SDRAM_MODE_2)..................... 9-23
DDR SDRAM Mode Control Register (DDR_SDRAM_MD_CNTL)................. 9-24
DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) ................. 9-26
DDR SDRAM Data Initialization (DDR_DATA_INIT) ....................................... 9-27
DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL) ............................. 9-27
DDR Initialization Address (DDR_INIT_ADDR)................................................ 9-28
DDR IP Block Revision 1 (DDR_IP_REV1)........................................................ 9-28
DDR IP Block Revision 2 (DDR_IP_REV2)........................................................ 9-29
Supported DDR SDRAM Organizations............................................................... 9-33
Clock Distribution ................................................................................................. 9-42
DDR SDRAM Refresh Timing.............................................................................. 9-45
DDR SDRAM Refresh and Power-Saving Modes ................................................ 9-45
Self-Refresh in Sleep Mode............................................................................... 9-47
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