MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 568
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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DMA/Messaging Unit
Table 12-8
12.3.7
This register contains the interrupt mask of the doorbell and message register events generated by the PCI
master.
Table 12-9
12-8
Offset 0x084
Reset
31–5
31–5
Bits
Bits
4
3
2
1
0
4
3
2
W
R
31
Figure 12-9
Name
IM1I
IM0I
Name
MCI
MCIM
IDI
IDIM
—
—
—
—
describes the IMISR register.
describes the IMISR register.
Inbound Message Interrupt Mask Register (IMIMR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Reserved
Machine check interrupt. Indicates whether a machine check interrupt condition was generated by setting the
IDR[31]. The interrupt is cleared by writing a 1 to IDR[IMC] from the CSB.
0 No machine check interrupt
1 There is a machine check interrupt
Inbound doorbell interrupt. Indicates whether an inbound doorbell interrupt occurred.
0 No inbound doorbell interrupt
1 There is an inbound doorbell interrupt
Reserved
Inbound message 1 interrupt. Indicates whether an inbound message 1 interrupt occurred. Write 1 to this
position to clear this bit.
0 No inbound message 1 interrupt.
1 There is an inbound message 1 interrupt.
position to clear this bit.
0 No inbound message 0 interrupt.
1 There is an inbound message 0 interrupt.
Inbound message 0 interrupt. Indicates whether an inbound message 0 interrupt occurred. Write 1 to this
Reserved
Machine check interrupt mask.
0 Machine check interrupt from the IDR is allowed
1 Machine check interrupt is masked. IMISR[MC1] is cleared
Inbound doorbell interrupt mask.
0 Inbound doorbell interrupt is allowed
1 Inbound doorbell interrupt is masked. IMISR[IDI] is cleared.
Reserved
shows the IMIMR fields.
Figure 12-9. Inbound Message Interrupt Mask Register (IMIMR)
Table 12-9. IMIMR Field Descriptions
Table 12-8. IMISR Field Descriptions
—
All zeros
Descriptions
Description
4
Access: User Read/Write
Freescale Semiconductor
MCIM IDIM — IM1IM
3
2
1
0
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