HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 175
HD64F3029XBL25V
Manufacturer Part Number
HD64F3029XBL25V
Description
MCU 5V 512K,PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.HD64F3029X25.pdf
(1012 pages)
Specifications of HD64F3029XBL25V
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Table 6.4
Area
8-bit
access
area
16-bit
access
area
Notes: 1. Undetermined data means that unpredictable data is output.
6.4.4
The initial state of each area is basic bus interface, three-state access space. The initial bus width
is selected according to the operating mode. The bus specifications described here cover basic
items only, and the following sections should be referred to for further details: Sections 6.4, Basic
Bus Interface, 6.5, DRAM Interface, and 6.8, Burst ROM Interface.
Area 0: Area 0 includes on-chip ROM, and in ROM-disabled expansion mode, all of area 0 is
external space. In ROM-enabled expansion mode, the space excluding on-chip ROM is external
space.
When area 0 external space is accessed, the CS
Either basic bus interface or burst ROM interface can be selected for area 0.
The size of area 0 is 128 kbytes in modes 1 and 2, and 2 Mbytes in modes 3, 4, and 5.
Areas 1 and 6: In external expansion mode, areas 1 and 6 are entirely external space.
When area 1 and 6 external space is accessed, the CS
output.
Only the basic bus interface can be used for areas 1 and 6.
The size of areas 1 and 6 is 128 kbytes in modes 1 and 2, and 2 Mbytes in modes 3, 4, and 5.
Rev. 2.0, 06/04, page 146 of 980
2. Invalid means that the bus is in the input state and the input is ignored.
Memory Areas
Access
Size
Byte
Byte
Word
Data Buses Used and Valid Strobes
Read/Write
Read
Write
Read
Write
Read
Write
Address
—
—
Even
Odd
Even
Odd
—
—
0
Valid Strobe
RD
HWR
RD
HWR
LWR
RD
HWR, LWR
signal can be output.
1
and CS
6
Upper Data Bus
(D
Valid
Valid
Invalid
Valid
Undetermined
data
Valid
Valid
pin signals respectively can be
15
to D
8
)
Lower Data Bus
(D
Invalid
Undetermined
data
Invalid
Valid
Undetermined
data
Valid
Valid
Valid
7
to D
0
)
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