HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 40

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Type
Data bus
Bus control CS
DRAM
interface
DMA
controller
(DMAC)
Symbol
D
CS
AS
RD
HWR
LWR
WAIT
RFSH
CS
CS
RD
HWR
UCAS
LWR
LCAS
DREQ
DREQ
TEND
TEND
15
7
0
2
5
to D
to
to
1
0
1
0
,
,
0
FP-100B
TFP-100B I/O
34 to 23,
21 to 18
2 to 5,
88 to 91
69
70
71
72
58
87
89, 88,
5, 4
70
71
6
72
7
5, 3
94, 93
Pin No.
Input/
output
Output Chip select: Select signals for areas 7 to 0
Output Address strobe: Goes low to indicate valid address
Output Read: Goes low to indicate reading from the external
Output High write: Goes low to indicate writing to the
Output Low write: Goes low to indicate writing to the
Input
Output Refresh: Indicates a refresh cycle
Output Row address strobe RAS
Output Write enable WE
Output Upper column address strobe UCAS
Output Lower column address strobe LCAS
Input
Output Transfer end 1 and 0: These signals indicate that
Name and Function
Data bus: Bidirectional data bus
output on the address bus
address space
external address space; indicates valid data on the
upper data bus (D
external address space; indicates valid data on the
lower data bus (D
Wait: Requests insertion of wait states in bus cycles
during access to the external address space
signal for DRAM
address strobe signal for DRAM
address strobe signal for DRAM
DMA request 1 and 0: DMAC activation
requests
the DMAC has ended a data transfer
WE: Write enable signal for DRAM
WE
WE
7
15
to D
to D
Rev. 2.0, 06/04, page 11 of 980
RAS: Row address strobe
RAS
RAS
0
).
8
).
UCAS
UCAS
UCAS: Column
LCAS: Column
LCAS
LCAS