HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 264

MCU 5V 512K,PB-FREE 100-TQFP

HD64F3029XBL25V

Manufacturer Part Number
HD64F3029XBL25V
Description
MCU 5V 512K,PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD64F3029XBL25V

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
7.4.7
The DMAC can be activated by an internal interrupt, external request, or auto-request. The
available activation sources differ depending on the transfer mode and channel as indicated in
table 7.11.
Table 7.11 DMAC Activation Sources
Activation Source
Internal
interrupts
External
requests
Auto-request
Activation by Internal Interrupts: When an interrupt request is selected as a DMAC activation
source and the DTE bit is set to 1, that interrupt request is not sent to the CPU. It is not possible
for an interrupt request to activate the DMAC and simultaneously generate a CPU interrupt.
When the DMAC is activated by an interrupt request, the interrupt request flag is cleared
automatically. If the same interrupt is selected to activate two or more channels, the interrupt
request flag is cleared when the highest-priority channel is activated, but the transfer request is
held pending on the other channels in the DMAC, which are activated in their priority order.
DMAC Activation
IMIA0
IMIA1
IMIA2
ADI
TXI0
RXI0
Falling edge
of DREQ
Low input at
DREQ
Channels
0A and 1A
Short Address Mode
Channels
0B and 1B
Rev. 2.0, 06/04, page 235 of 980
Normal
Full Address Mode
Block

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