HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 993

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev. 2.0, 06/04, page 964 of 980
*9 When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control
*10 When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control
*11 When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control
*12 When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control
*13 When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control
*14 When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control
*15 When any of bits DRAS2, DRAS1, or DRAS0 in DRCRA (DRAM control register A) is
*16 When any of bits DRAS2, DRAS1, or DRAS0 in DRCRA (DRAM control register A) is
register A) is 101.
register A) is other than 101, and bit CS5E in CSCR (chip select control register) is set
to 1.
register A) is other than 101, and bit CS5E in CSCR (chip select control register) is
cleared to 0.
register A) is 100, 101, or 110.
register A) is other than 100, 101, or 110, and bit CS4E in CSCR (chip select control
register) is set to 1.
register A) is other than 100, 101, or 110, and bit CS4E in CSCR (chip select control
register) is cleared to 0.
set to 1, and bit CSEL in DRCRB (DRAM control register B) is cleared to 0.
set to 1, and bit CSEL in DRCRB (DRAM control register B) is set to 1; or, when bits
DRAS2, DRAS1, and DRAS0 are all cleared to 0.