HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 586

MCU 5V 512K,PB-FREE 100-TQFP

HD64F3029XBL25V

Manufacturer Part Number
HD64F3029XBL25V
Description
MCU 5V 512K,PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD64F3029XBL25V

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
15.4.3
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input at a time t
conversion timing. Table 15.4 indicates the A/D conversion time.
As indicated in figure 15.5, the A/D conversion time includes t
length of t
time therefore varies within the ranges indicated in table 15.4.
In scan mode, the values given in table 15.4 apply to the first conversion. In the second and
subsequent conversions the conversion time is fixed at 128 states when CKS = 0 or 66 states when
CKS = 1.
Address bus
Write signal
Input sampling
timing
ADF
Legend
(1):
(2):
t :
t
t
D
SPL
CONV
:
Input Sampling and A/D Conversion Time
:
D
ADCSR write cycle
ADCSR address
A/D conversion start delay time
Input sampling time
A/D conversion time
varies depending on the timing of the write access to ADCSR. The total conversion
D
after the ADST bit is set to 1, then starts conversion. Figure 15.5 shows the A/D
(1)
(2)
t
D
Figure 15.5 A/D Conversion Timing
t
SPL
t
CONV
D
and the input sampling time. The
Rev. 2.0, 06/04, page 557 of 980

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