HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 201

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Use the RLW bit in DRCRB to adjust the RAS signal width. A single refresh wait state (T
) can
RW
be inserted between the T
state and T
state by setting the RLW bit to 1.
R1
R2
The RLW bit setting is valid only for CBR refresh cycles, and does not affect DRAM read/write
cycles. The number of states in the CBR refresh cycle is not affected by the settings in ASTCR,
WCRH, or WCRL, or by the state of the WAIT pin.
Figure 6.29 shows the timing when the TPC bit and RLW bit are both set to 1.
T
T
T
T
T
Rp1
RP2
R1
RW
R2
Address bus*
Area 2 start address
(
)
n
PB
/PB
4
5
(
/
)
(
)
High
High level
Note: * In address update mode 1, the area 2 start address is output.
In address update mode 2, the address in the preceding bus cycle is retained.
Figure 6.29 CBR Refresh Timing (CSEL = 0, TPC = 1, RLW = 1)
DRAM must be refreshed immediately after powering on in order to stabilize its internal state.
When using the H8/3029 CAS-before-RAS refresh function, therefore, a DRAM stabilization
period should be provided by means of interrupts by another timer module, or by counting the
number of times bit 7 (CMF) of RTMCSR is set, for instance, immediately after bits DRAS2 to
DRAS0 have been set in DRCRA.
Self-Refreshing: A self-refresh mode (battery backup mode) is provided for DRAM as a kind of
standby mode. In this mode, refresh timing and refresh addresses are generated within the
DRAM. The H8/3029 has a function that places the DRAM in self-refresh mode when the chip
enters software standby mode.
Rev. 2.0, 06/04, page 172 of 980