HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 23

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10.5 Interrupt ............................................................................................................................ 403
10.6 8-Bit Timer Application Example..................................................................................... 404
10.7 Usage Notes ...................................................................................................................... 405
Section 11 Programmable Timing Pattern Controller (TPC) ............................415
11.1 Overview........................................................................................................................... 415
11.2 Register Descriptions ........................................................................................................ 419
11.3 Operation .......................................................................................................................... 432
11.4 Usage Notes ...................................................................................................................... 439
Rev. 2.0, 06/04, page xviii of xxiv
10.4.6 Input Capture Setting ........................................................................................... 402
10.5.1 Interrupt Sources.................................................................................................. 403
10.5.2 A/D Converter Activation.................................................................................... 404
10.7.1 Contention between 8TCNT Write and Clear...................................................... 405
10.7.2 Contention between 8TCNT Write and Increment .............................................. 406
10.7.3 Contention between TCOR Write and Compare Match ...................................... 407
10.7.4 Contention between TCOR Read and Input Capture ........................................... 408
10.7.5 Contention between Counter Clearing by Input Capture and
10.7.6 Contention between TCOR Write and Input Capture .......................................... 410
10.7.7 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode
10.7.8 Contention between Compare Matches A and B ................................................. 412
10.7.9 8TCNT Operation and Internal Clock Source Switchover .................................. 412
11.1.1 Features................................................................................................................ 415
11.1.2 Block Diagram ..................................................................................................... 416
11.1.3 TPC Pins .............................................................................................................. 417
11.1.4 Registers............................................................................................................... 418
11.2.1 Port A Data Direction Register (PADDR) ........................................................... 419
11.2.2 Port A Data Register (PADR) .............................................................................. 419
11.2.3 Port B Data Direction Register (PBDDR)............................................................ 420
11.2.4 Port B Data Register (PBDR) .............................................................................. 420
11.2.5 Next Data Register A (NDRA) ............................................................................ 421
11.2.6 Next Data Register B (NDRB)............................................................................. 423
11.2.7 Next Data Enable Register A (NDERA).............................................................. 425
11.2.8 Next Data Enable Register B (NDERB) .............................................................. 426
11.2.9 TPC Output Control Register (TPCR) ................................................................. 427
11.2.10 TPC Output Mode Register (TPMR) ................................................................... 430
11.3.1 Overview.............................................................................................................. 432
11.3.2 Output Timing...................................................................................................... 433
11.3.3 Normal TPC Output............................................................................................. 434
11.3.4 Non-Overlapping TPC Output............................................................................. 436
11.3.5 TPC Output Triggering by Input Capture ............................................................ 438
11.4.1 Operation of TPC Output Pins ............................................................................. 439
Counter Increment ............................................................................................... 409
(Cascaded Connection) ........................................................................................ 411