HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 670

MCU 5V 512K,PB-FREE 100-TQFP

HD64F3029XBL25V

Manufacturer Part Number
HD64F3029XBL25V
Description
MCU 5V 512K,PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD64F3029XBL25V

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
18.9.2
Table 18.12 shows the settings for the operating modes of PROM mode, and table 18.13 lists the
commands used in PROM mode. The following sections provide detailed information on each
mode.
Table 18.12 Settings for Each Operating Mode of PROM Mode
Mode
Read
Output disable
Command write
Chip disable
Notes: 1. The chip-disable mode is not a standby state; internally, it is an operational state.
Memory-read mode: This mode supports reading, in units of bytes, from the user MAT or user
boot MAT.
Auto-program mode: This mode supports the simultaneous programming of the user MAT and
user boot MAT in 128-byte units. Status polling is used to confirm the end of automatic
programming.
Auto-erase mode: This mode only supports the automatic erasing of the entire user MAT or
user boot MAT. Status polling is used to confirm the end of automatic erasing.
Status-read mode: Status polling is used with automatic programming and automatic erasure.
Normal completion can be detected by reading the signal on the I/O6 pin. In status-read mode,
error information is output when an error has occurred.
2. To write commands when making a transition to the auto-program or auto-erase mode,
* Ain indicates that there is also an address input in auto-program mode.
PROM Mode Operation
input a high-level signal on the FWE pin.
FWE
H or L
H or L
H or L
H or L
CE
CE
L
L
L
H
CE
CE
OE
OE
L
H
H
X
OE
OE
Pin Name
WE
WE
H
H
L
X
WE
WE
Rev. 2.0, 06/04, page 641 of 980
I/O7 to 0
Data output
Hi-Z
Data input
Hi-Z
X
X
A18 to 0
Ain
*Ain

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