HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 32

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Table 1.1
Feature
CPU
Memory
Interrupt
controller
Bus controller
Features
Description
Upward-compatible with the H8/300 CPU at the object-code level
General-register machine
High-speed operation
16-Mbyte address space
Instruction features
H8/3029
Sixteen 16-bit general registers
(also usable as sixteen 8-bit registers, eight 16-bit registers, or eight 32-bit
registers)
Maximum clock rate: 25 MHz
Add/subtract: 80 ns
Multiply/divide: 560 ns
8/16/32-bit data transfer, arithmetic, and logic instructions
Signed and unsigned multiply instructions (8 bits x 8 bits, 16 bits x 16 bits)
Signed and unsigned divide instructions (16 bits ÷ 8 bits, 32 bits ÷ 16 bits)
Bit accumulator function
Bit manipulation instructions with register-indirect specification of bit
positions
ROM: 512 kbytes
RAM: 16 kbytes
Seven external interrupt pins: NMI, IRQ0 to IRQ5
36 internal interrupts
Three selectable interrupt priority levels
Address space can be partitioned into eight areas, with independent bus
specifications in each area
Chip select output available for areas 0 to 7
8-bit access or 16-bit access selectable for each area
Two-state or three-state access selectable for each area
Selection of two wait modes
Number of program wait states selectable for each area
Direct connection of burst ROM
Direct connection of up to 8-Mbyte DRAM (or DRAM interface can be used
as interval timer)
Bus arbitration function
Rev. 2.0, 06/04, page 3 of 980