HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 189

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Table 6.7
Pin
PB4
PB5
HWR
LWR
CS
CS
CS
CS
RD
P80
A
D
Note:
6.5.6
Figure 6.18 shows the basic access timing for DRAM space. The basic DRAM access timing is
four states: one precharge cycle (T
address output cycle (T
ASTCR control only enabling or disabling of wait insertion between T
the number of access states. When the corresponding bit in ASTCR is cleared to 0, wait states
cannot be inserted between T
If a DRAM read/write cycle is followed by an access cycle for an external area other than DRAM
space when HWR and LWR are selected as the UCAS and LCAS output pins, an idle cycle (Ti) is
inserted unconditionally immediately after the DRAM access cycle. See section 6.9, Idle Cycle,
for details.
Rev. 2.0, 06/04, page 160 of 980
12
15
2
3
4
5
to A
to D
0
0
* Fixed high in a read access.
With DRAM
Designated Name
UCAS
LCAS
UCAS
LCAS
RAS
RAS
RAS
RAS
WE
RFSH
A
D
Basic Timing
12
15
to A
DRAM Interface Pins
to D
2
3
4
5
0
0
c1
Upper column
address strobe
Lower column
address strobe
Upper column
address strobe
Lower column
address strobe
Row address
strobe 2
Row address
strobe 3
Row address
strobe 4
Row address
strobe 5
Write enable
Refresh
Address
Data
, T
c2
) states. Unlike the basic bus interface, the corresponding bits in
c1
and T
p
) state, one row address output cycle (T
c2
in the DRAM access cycle.
I/O
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
I/O
Function
Upper column address strobe for DRAM
space access (when CSEL = 0 in DRCRB)
Lower column address strobe for DRAM
space access (when CSEL = 0 in DRCRB)
Upper column address strobe for DRAM
space access (when CSEL = 1 in DRCRB)
Lower column address strobe for DRAM
space access (when CSEL = 1 in DRCRB)
access
access
access
access
access*
output
Row address strobe for DRAM space
Row address strobe for DRAM space
Row address strobe for DRAM space
Row address strobe for DRAM space
Write enable for DRAM space write
Goes low in refresh cycle
Row address/column address multiplexed
Data input/output pins
c1
and T
r
) state, and two column
c2
, and do not affect