HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 541

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Receive Error Flags and Transmitter Operation (Synchronous Mode Only): When a receive
error flag (ORER, PER, or FER) is set to 1 the SCI will not start transmitting, even if the TDRE
flag is cleared to 0. Be sure to clear the receive error flags to 0 when starting to transmit. Note
that clearing the RE bit to 0 does not clear the receive error flags to 0.
Receive Data Sampling Timing in Asynchronous Mode and Receive Margin: In asynchronous
mode the SCI operates on a base clock with 16 times the bit rate frequency. In receiving, the SCI
synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive
data is latched at the rising edge of the eighth base clock pulse. See figure 13.21.
Internal base clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
The receive margin in asynchronous mode can therefore be expressed as shown in equation (1).
Rev. 2.0, 06/04, page 512 of 980
M =
M:
N:
D:
L:
F:
Figure 13.21 Receive Data Sampling Timing in Asynchronous Mode
Receive margin (%)
Ratio of clock frequency to bit rate (N = 16)
Clock duty cycle (L = 0 to 1.0)
Frame length (L = 9 to 12)
Absolute deviation of clock frequency
(0.5
0
Start bit
–
8 clocks
2N
1
16 clocks
)
–
7
(L
–
0.5) F
–
15 0
D
–
N
0.5
D
(1 + F)
0
. . . . . . . . (1)
7
100%
15 0
D
1