HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 556

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5. If the transmitting device does not receive an error signal, it proceeds to transmit the next data
14.3.4
Table 14.3 shows a bit map of the registers used in the smart card interface. Bits indicated as 0 or
1 must be set to the value shown. The setting of other bits is described in this section.
Table 14.3 Smart Card Interface Register Settings
Register Address*
SMR
BRR
SCR
TDR
SSR
RDR
SCMR
Notes: — Unused bit.
Serial Mode Register (SMR) Settings: Clear the GM bit to 0 when using the normal smart card
interface mode, or set to 1 when using GSM mode. Clear the O/E bit to 0 if the smart card is of the
direct convention type, or set to 1 if of the inverse convention type.
Bits CKS1 and CKS0 select the clock source of the built-in baud rate generator. See section
14.3.5, Clock.
Bit Rate Register (BRR) Settings: BRR is used to set the bit rate. See section 14.3.5, Clock, for
the method of calculating the value to be set.
Serial Control Register (SCR) Settings: The TIE, RIE, TE, and RE bits have their normal serial
communication functions. See section 13, Serial Communication Interface, for details. The CKE1
and CKE0 bits specify clock output. To disable clock output, clear these bits to 00; to enable clock
output, set these bits to 01. Clock output is not performed when the GM bit is set to 1 in SMR.
Clock output can also be fixed low or high.
frame. If it receives an error signal, however, it returns to step 2 and transmits the same data
again.
*1 Lower 20 bits of the address in advanced mode.
*2 When GM is cleared to 0 in SMR, the CKE1 bit must also be cleared to 0.
Register Settings
H'FFFB0
H'FFFB1
H'FFFB2
H'FFFB3
H'FFFB4
H'FFFB5
H'FFFB6
1
BRR7
TDR7
TDRE
RDR7
—
Bit 7
GM
TIE
BRR6
—
Bit 6
0
RIE
TDR6
RDRF
RDR6
Bit 5
1
BRR5
TE
TDR5
ORER
RDR5
—
Bit 4
O/E
BRR4
RE
TDR4
ERS
RDR4
—
Bit
Bit 3
1
BRR3
0
TDR3
PER
RDR3
SDIR
Rev. 2.0, 06/04, page 527 of 980
Bit 2
0
BRR2
0
TDR2
RDR2
SINV
TEND
Bit 1
CKS1
BRR1
CKE1*
TDR1
0
RDR1
—
2
Bit 0
CKS0
BRR0
CKE0
TDR0
0
RDR0
SMIF