HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 730

MCU 5V 512K,PB-FREE 100-TQFP

HD64F3029XBL25V

Manufacturer Part Number
HD64F3029XBL25V
Description
MCU 5V 512K,PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD64F3029XBL25V

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
20.2.2
MSTCRH is an 8-bit readable/writable register that controls output of the system clock ( ). It also
controls the module standby function, which places individual on-chip supporting modules in the
standby state. Module standby can be designated for the SCI0, SCI1, SCI2.
In modes 1 to 5, MSTCRH is initialized to H'78 by a reset and in hardware standby mode, while
in mode 7 it is initialized to H'F8. It is not initialized in software standby mode.
Bit 7— Clock Stop (PSTOP): Enables or disables output of the system clock ( ).
Bit 1
PSTOP
0
1
Bits 6 to 3—Reserved: These bits cannot be modified and are always read as 1.
Bit 2—Module Standby H2 (MSTPH2): Selects whether to place the SCI2 in standby.
Bit 2
MSTPH2
0
1
Bit
Modes 1 to 5 : Initial value
Mode 7 : Initial value
Read/Write
Module Standby Control Register H (MSTCRH)
Description
System clock output is enabled
System clock output is disabled
Description
SCI2 operates normally
SCI2 is in standby state
PSTOP
Enables or disables
output of the system clock
R/W
clock stop
7
0
1
6
1
1
Reserved bit
5
1
1
(Initial value : When modes 1 to 5 are selected)
(Initial value : When mode 7 is selected)
4
1
1
3
1
1
Rev. 2.0, 06/04, page 701 of 980
MSTPH2
Module standby H2 to 0
These bits select modules
to be placed in standby
R/W
2
0
0
MSTPH1
R/W
1
0
0
(Initial value)
MSTPH0
R/W
0
0
0

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