HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 218
HD64F3029XBL25V
Manufacturer Part Number
HD64F3029XBL25V
Description
MCU 5V 512K,PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.HD64F3029X25.pdf
(1012 pages)
Specifications of HD64F3029XBL25V
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from
ROM and the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented.
External Address Space Access Immediately after DRAM Space Access: If a DRAM space
access is followed by a non-DRAM external access when HWR and LWR have been selected as
the UCAS and LCAS output pins by means of the CSEL bit in DRCRB, a T
regardless of the settings of bits ICIS0 and ICIS1 in BCR. Figure 6.45 shows an example of the
operation.
This is done to prevent simultaneous changing of the HWR and LWR signals used as UCAS and
LCAS in DRAM space and CSn for the space in the next cycle, and so avoid an erroneous write to
the external device in the next cycle.
A T
pins.
In the case of consecutive DRAM space access precharge cycles (T
invalid. In the case of consecutive reads between different areas, for example, if the second
access is a DRAM access, only a T
is shown in figure 6.46.
i
cycle is not inserted when PB
Address bus
Data bus
094
4,
Figure 6.44 Example of Idle Cycle Operation (2) (ICIS0 = 1)
(a) Idle cycle not inserted
Bus cycle A Bus cycle B
T
1
T
2
Long buffer-off
T
3
time
4
T
p
and PB
1
cycle is inserted, and a T
T
2
5
Data
collision
have been selected as the UCAS and LCAS output
Address bus
Data bus
094
4,
i
cycle is not. The timing in this case
Rev. 2.0, 06/04, page 189 of 980
(b) Idle cycle inserted
Bus cycle A Bus cycle B
T
p
), the ICIS0 bit settings are
1
T
2
T
i
3
cycle is inserted
T
i
T
1
T
2
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