HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 24

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 12 Watchdog Timer ..............................................................................441
12.1 Overview........................................................................................................................... 441
12.2 Register Descriptions ........................................................................................................ 443
12.3 Operation .......................................................................................................................... 449
12.4 Interrupts........................................................................................................................... 453
12.5 Usage Notes ...................................................................................................................... 453
Section 13 Serial Communication Interface ......................................................455
13.1 Overview........................................................................................................................... 455
13.2 Register Descriptions ........................................................................................................ 460
13.3 Operation .......................................................................................................................... 483
13.4 SCI Interrupts.................................................................................................................... 510
13.5 Usage Notes ...................................................................................................................... 510
11.4.2 Note on Non-Overlapping Output ....................................................................... 439
12.1.1 Features................................................................................................................ 441
12.1.2 Block Diagram ..................................................................................................... 442
12.1.3 Register Configuration......................................................................................... 442
12.2.1 Timer Counter (TCNT)........................................................................................ 443
12.2.2 Timer Control/Status Register (TCSR) ................................................................ 444
12.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 446
12.2.4 Notes on Register Access..................................................................................... 447
12.3.1 Watchdog Timer Operation ................................................................................. 449
12.3.2 Interval Timer Operation ..................................................................................... 450
12.3.3 Timing of Setting of Overflow Flag (OVF)......................................................... 451
12.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) .................................. 452
13.1.1 Features................................................................................................................ 455
13.1.2 Block Diagram ..................................................................................................... 457
13.1.3 Input/Output Pins................................................................................................. 458
13.1.4 Register Configuration......................................................................................... 459
13.2.1 Receive Shift Register (RSR)............................................................................... 460
13.2.2 Receive Data Register (RDR) .............................................................................. 460
13.2.3 Transmit Shift Register (TSR) ............................................................................. 461
13.2.4 Transmit Data Register (TDR)............................................................................. 461
13.2.5 Serial Mode Register (SMR)................................................................................ 462
13.2.6 Serial Control Register (SCR).............................................................................. 466
13.2.7 Serial Status Register (SSR)................................................................................. 471
13.2.8 Bit Rate Register (BRR)....................................................................................... 476
13.3.1 Overview.............................................................................................................. 483
13.3.2 Operation in Asynchronous Mode ....................................................................... 485
13.3.3 Multiprocessor Communication........................................................................... 495
13.3.4 Synchronous Operation........................................................................................ 501
13.5.1 Notes on Use of SCI ............................................................................................ 510
Rev. 2.0, 06/04, page xix of xxiv