HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 287

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

8.2
8.2.1
Port 1 is an 8-bit input/output port also used for address output, with the pin configuration shown
in figure 8.1. The pin functions differ between the expanded modes with on-chip ROM disabled,
expanded modes with on-chip ROM enabled, and single-chip mode. In modes 1 to 4 (expanded
modes with on-chip ROM disabled), they are address bus output pins (A
In mode 5 (expanded mode with on-chip ROM enabled), settings in the port 1 data direction
register (P1DDR) can designate pins for address bus output (A
(single-chip mode), port 1 is a generic input/output port.
When DRAM is connected to areas 2 to 5, A
write cycles. For details see section 6.5, DRAM Interface.
Pins in port 1 can drive one TTL load and a 90-pF capacitive load. They can also drive an LED or
a darlington transistor pair.
Rev. 2.0, 06/04, page 258 of 980
Port 1
Port 1
Overview
Port 1 pins
P1 /A
P1 /A
P1 /A
P1 /A
P1 /A
P1 /A
P1 /A
P1 /A
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Figure 8.1 Port 1 Pin Configuration
Modes 1 to 4
A (output)
A (output)
A (output)
A (output)
A (output)
A (output)
A (output)
A (output)
7
6
5
4
3
2
1
0
7
to A
0
output row and column addresses in read and
Mode 5
P1 (input)/A (output)
P1 (input)/A (output)
P1 (input)/A (output)
P1 (input)/A (output)
P1 (input)/A (output)
P1 (input)/A (output)
P1 (input)/A (output)
P1 (input)/A (output)
7
6
5
4
3
2
1
0
7
to A
7
6
5
4
3
2
1
0
0
) or generic input. In mode 7
7
to A
0
Mode 7
P1 (input/output)
P1 (input/output)
P1 (input/output)
P1 (input/output)
P1 (input/output)
P1 (input/output)
P1 (input/output)
P1 (input/output)
).
7
6
5
4
3
2
1
0