HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 186

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.5
6.5.1
The H8/3029 is provided with a DRAM interface with functions for DRAM control signal (RAS,
UCAS, LCAS, WE) output, address multiplexing, and refreshing, that direct connection of
DRAM. In the expanded modes, external address space areas 2 to 5 can be designated as DRAM
space accessed via the DRAM interface. A data bus width of 8 or 16 bits can be selected for
DRAM space by means of a setting in ABWCR. When a 16-bit data bus width is selected, CAS is
used for byte access control. In the case of
type can be connected. A fast page mode is supported in addition to the normal read and write
access modes.
6.5.2
Designation of areas 2 to 5 as DRAM space, and selection of the RAS output pin for each area
designated as DRAM space, is performed by setting bits in DRCRA. Table 6.5 shows the
correspondence between the settings of bits DRAS2 to DRAS0 and the selected DRAM space and
RAS output pin.
When an arbitrary value has been set in DRAS2 to DRAS0, a write of a different value other than
000 must not be performed.
DRAM Interface
Overview
DRAM Space and RAS
RAS
RAS
RAS Output Pin Settings
16-bit organization DRAM, therefore, the 2-CAS
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