tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 100

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Exceptions/Interrupts
Cause
(No.13)
6.6.2.3
(Note 1) An interrupt vector address differs depending on combination of the BEV bit in the Status
(Note 3) The value in this field is undefined for any other exception.
(Note 2) The processor updates the BD bit only if the EXL bit is 0 when an interrupt or exception
register and the IV bit in the Cause register. See Note 4 in the Status register section.
occurred.
Cause Register
The Cause register indicates the cause of the last exception.
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
Interrupt Request (Hardware)
Interrupt
vector
1:Different
from
exception
vector
0:Same as
exception
vector
(Note 1)
Set when
an
exception
occurred
in a jump
or branch
delay slot.
(Note 2)
Interrupt level is set in IP[4:2] when hardware interrupt is requested.
“0” is read. Exception code
Undefine
Undefine
Undefine
R/W
IP7
15
23
31
BD
IV
7
R
R
R
0
d
d
d
“0” is read.
00000: Interrupt (software and hardware)
00100: Address Error (instruction fetch or load)
00101: Address Error (store access)
00110: Bus Error (instruction fetch)
00111: Bus Error (data access: load)
01000: System Call exception
01001: Breakpoint exception
01010: Reserved Instruction exception
01011: Coprocessor Unusable exception
01100: Integer Overflow exception
01101: Trap exception
Undefine
IP6
WP
14
22
30
6
R
R
R
0
d
0
0
TMP19A44(rev1.3) 6-50
Indicates
coprocessor
number
when a
Coprocessor
Unusable
was taken.
(Note 3)
Undefine
CE1
IP5
13
21
29
5
R
0
d
0
Undefined
R
referenced
exception
ExcCode
Undefine
CE0
IP4
12
20
28
R
4
R
0
d
0
unit
the
“0” is read.
“0” is read.
Undefine
IP3
11
19
27
R
3
0
d
0
0
R
Undefine
IP2
10
18
26
R
2
0
d
0
0
R
TMP19A44
“0” is read.
Interrupt
(Software)
Write
software interrupt.
Undefine
R/W
IP1
17
25
1
9
0
0
d
0
“1”
2010-04-01
R
for
Undefine
Request
R/W
IP0
16
24
0
8
0
d
0
0
using