tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 289

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

DMA Controller (DMAC)
10.4.4
A channel is activated if the Str bit of the CCRn of a channel is set to "1." If a channel is activated, an
activation check is conducted and if no error is detected, the channel is put into a standby mode.
If a transfer request is generated when a channel is in a standby mode, the DMAC acquires bus control
authority and starts to transfer data.
Channel operation is completed either normally or abnormally (forced termination or occurrence of an
error). Either normal completion or abnormal completion is indicated to the CSRn.
Start of channel operation
Completion of channel operation
Normal completion
Abnormal completion
A channel is activated if the Str bit of the CCRn is set to "1."
When a channel is activated, a configuration error check is conducted and if no error is detected,
the channel is put into a standby mode. If an error is detected, the channel is deactivated and this
state of completion is considered to be abnormal completion. When a channel goes into a standby
mode, the Act bit of the CSRn of that channel becomes "1."
If a channel is programmed to start operation in response to an internal transfer request, a transfer
request is generated immediately and the DMAC acquires bus control authority and starts to
transfer data. If a channel is programmed to start operation in response to an external transfer
request, the DMAC acquires bus control authority after INTDREQn or DREQn is asserted, and
starts to transfer data.
A channel completes operation either normally or abnormally and either one of these states is
indicated to the CSRn.
If an attempt is made to set the Str bit of the CCRn register to "1" when the NC or AbC bit of the
CSRn register is "1," channel operation does not start and the completion of operation is
considered to be abnormal completion.
Channel operation is considered to have been completed normally in the case shown below. For
channel operation to be considered to have been completed normally, the transfer of a unit of data
(value specified in the TrSiz field of CCRn) must be completed successfully.
•
Cases of abnormal completion of DMAC operation are as follows:
•
Channel Operation
When the contents of BCRn become 0 and data transfer is completed
Completion due to a configuration error
A configuration error occurs if there is a mistake in the DMA transfer setting. Because a
configuration error occurs before data transfer begins, values specified in SARn, DARn and
BCRn remain the same as when they were initially specified. If channel operation is
completed abnormally due to a configuration error, the AbC bit of the CSRn is set to "1,"
along with the Conf bit. Causes of a configuration error are as follows:
−
−
−
−
The Str bit of CCRn was set to "1" when the NC bit or AbC bit of CSRn was "1."
A value that is not an integer multiple of the unit of data was set for BCRn.
A value that is not an integer multiple of the unit of data was set for SARn or DARn.
The Str bit of CCRn was set to "1" when the BCRn value was "0."
TMP19A44 (rev1.3) 10-26
TMP19A44
2010-04-01