tmp19a44fda TOSHIBA Semiconductor CORPORATION, tmp19a44fda Datasheet - Page 78

• Manufacturer Part Number: tmp19a44fda
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Exceptions/Interrupts
6.5.1.6
6.5.1.7
6.5.1.8
6.5.1.9
Active State
Priority
Factors for clearing standby mode
DMAC activation by interrupt
interrupt level is selected.
interrupt number is prioritized.
designate a certain level.
interrupt to clear standby mode, the active state must be set to “H” level. See the next section for details.
corresponding CG control register name.
an active state to the IMCG<EMCG> bit. The active state is selectable from the “H” level, “L” level, rising
edge, falling edge or both edges.
controller register must be set to “H”. Setting the active state to “H” level allows INTC to receive a signal in
“H” level after CG detects an interrupt.
the active level condition is satisfied. To use an interrupt as the DMAC activation, the corresponding DMAC
channel must be set in IMC<ILC>.
check whether a transfer is requested or not. Writing “1” to a bit that corresponding to the DMAC channel
can clear an transfer request.
the IMC<EIM> bit of the interrupt controller register.
The interrupt level to be applied is set by IMC<IL> of INTC. ”7” is the highest priority level.
If multiple factors are generated simultaneously, an interrupt with the highest priority based on the
If multiple factors with the same interrupt level are generated simultaneously, an interrupt with the smaller
In addition to the individual interrupt level, set an interrupt level of the entire INTC in the
ILEV<CMASK> bit of the INTC controller register. Interrupts with the lower priority than the specified
in the ILEV<CMASK> bit are suspended. Default setting of the ILEV<CMASK>bit is 000”. This setting
enables all the interrupt levels.
The active state indicates which change in signal of an interrupt factor triggers an interrupt. It can be set in
The active state is selectable from the “H” level, “L” level, rising or falling edge but some interrupt factors
As for the interrupt factors with specific conditions, configure as they are.
You can select a condition for the factor of which activation trigger in the Table is “Selectable”. To use an
The interrupts that can be used for clearing standby mode are shown in the Table 6.5 together with the
To use an interrupt for clearing standby mode, enable the IMCG<INTEN> bit of the CG register and set
When using an interrupt for clearing standby mode, an active state of the IMC<EIM> bit in the INTC
An interrupt factor can be used to activate DAMC. In this case, no interrupt is generated.
By setting the IMC<DM> bit of the INTC register to “1”, a request to start transfer is output to DMAC if
DREQFLG of the DMAC register is used to clear or monitor a transfer request. Reading this register can
See “Chapter 10 DMA Controller“ for details.
Each of interrupt factors can be individually set to one of the seven interrupt priority levels by INTC.
TMP19A44(rev1.3) 6-28
TMP19A44
2010-04-01